Applying epitaxial silicon in disposable spacer flow

1. A method of fabricating transistors on a semiconductor substrate comprising:

forming transistor gates of first and second transistors located in first and second areas of the semiconductor substrate, respectively, wherein the transistor gates have generally vertical sidewalls;

simultaneously forming source and drain regions for the first and second transistors;

forming temporary spacers on the vertical sidewalls of the first and second transistor gates, wherein the temporary spacers of the first transistor abut a semiconductor structure such that the source and drain regions of the first transistor are vertically covered, and wherein the temporary spacers of the second transistor cover a portion of the source and drain regions of the second transistor such that a portion of the source and drain regions remain exposed; and

exposing the semiconductor substrate to an implant dopant to change the dopant level of the exposed portions of the source and drain regions of the second transistors.

2. The method of claim 1 , further comprising:

forming epitaxial regions above the exposed portions of the source and drain regions of the second transistors.