Synchronization system and related integrated circuit
View Patent ↗A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.
1. A system comprising a memory and a control circuit, wherein said control circuit comprises:
a write interface for writing data in said memory with a first clock signal, wherein said write interface is configured for operating with a write pointer in response to a write command;
a read interface for reading data from said memory with a second clock signal, wherein said read interface is configured for operating with a read pointer in response to a read command;
a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency; and
an elaboration circuit for elaborating data in said memory with an elaboration latency, said elaboration latency being smaller than said synchronization latency,
wherein the system is configured so that synchronization circuit and the elaboration circuit can perform the respective synchronizing and elaborating in parallel.
2. The system according to claim 1 , wherein said elaboration circuit is configured for:
receiving from a memory location in said memory the last data written to said memory via said write interface;
elaborating said last data received from said memory location; and
sending said elaborated last data to said memory location.
3. The system according to claim 1 , wherein said elaboration circuit is a combinational circuit.
4. The system according to claim 1 , wherein said elaboration circuit is a sequential circuit.
5. The system according to claim 4 , wherein said sequential circuit is driven by said first clock signal or a clock signal having a rate being equal to a multiple of the rate of said first clock signal.
6. The system according to claim 1 , wherein said memory comprises a dual port RAM memory, and wherein the first port of said memory is coupled to said control circuit, and the second port of said memory is coupled to said elaboration circuit.
7. The system according to claim 1 , wherein said synchronization circuit comprises at least one register for receiving as input said write pointer, and wherein said at least one register is drivable via said second clock signal.
8. The system according to claim 1 , wherein said write interface and said read interface comprise a respective counter.
9. The system according to claim 1 , wherein said control circuit is configured for managing said memory as a circular buffer, and wherein said control circuit comprises means for generating as a function of said write pointer and said read pointer a status signal, which indicates a condition in which said circular buffer is empty, and/or a status signal, which indicates a condition in which said circular buffer is full.
10. The system according to claim 1 , wherein said system comprises an integrated circuit.
11. A method of operating a system comprising a memory and a control circuit, comprising:
writing data in said memory with a first clock signal, wherein said write interface is configured for operating with a write pointer in response to a write command;
reading data from said memory with a second clock signal, wherein said read interface is configured for operating with a read pointer in response to a read command;
synchronizing said write pointer and said read pointer with a synchronization latency; and
elaborating data in said memory with an elaboration latency, said elaboration latency being smaller than said synchronization latency;
latency, said elaboration latency being smaller than said synchronization latency,
wherein the synchronizing and elaborating are performed in parallel.
12. The method of claim 11 further comprising:
receiving from a memory location in said memory the last data written to said memory via said write interface;
elaborating said last data received from said memory location; and
sending said elaborated last data to said memory location.
13. The method of claim 11 , wherein elaborating data is provided by a combinational circuit.
14. The method of claim 11 , wherein elaborating data is provided by a sequential circuit.
15. The method of claim 14 , wherein said sequential circuit is driven by said first clock signal or a clock signal having a rate being equal to a multiple of the rate of said first clock signal.
16. The method of claim 11 , wherein said memory comprises a dual port RAM memory.
17. The method of claim 11 , wherein said synchronizing is provided by at least one register for receiving as input said write pointer, and wherein said at least one register is drivable via said second clock signal.
18. The method of claim 11 , wherein said writing and reading are provided by a respective counter.
19. The method of claim 11 , further comprising managing said memory as a circular buffer, and generating as a function of said write pointer and said read pointer a status signal, which indicates a condition in which said circular buffer is empty, and/or a status signal, which indicates a condition in which said circular buffer is full.
20. The method of claim 11 , wherein said method is performed on an integrated circuit.