Content addressable memory
The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
1. A content addressable memory comprising:
a memory array including a plurality of memory cells arranged in a matrix and each memory cell row of the memory array storing entry data to be retrieved;
entry selecting means for selecting a corresponding entry in the memory array in accordance with a given entry designation signal;
pre-search means for generating an entry designation signal for designating a corresponding entry in the memory array in accordance with search data and supplying the entry designation signal to the entry selecting means;
a plurality of sense amplifier circuits for detecting and amplifying data stored in an entry selected by the entry selecting means on a sub-entry unit basis, each sense amplifier circuit being arranged for a respective column of said memory array; and
a comparing/logic processing circuit for receiving the search data and output data having a predetermined bit width of the sense amplifier circuit, comparing the search data and the output data having the predetermined bit width of the sense amplifier circuit, and generating a signal indicative of a result of the comparison.
2. The content addressable memory according to claim 1 , wherein the comparing/logic processing circuit includes:
a plurality of match determining circuits for determining a match between output data of the sense amplifier circuit and the search data, each match determining circuit being arranged for a respective column of said memory array.