IP Library › Granted Patent US 8,599,998
Granted Patent B2
US 8,599,998 · App. 13/025,479 · Granted Dec 3, 2013

Display device, semiconductor device, and driving method thereof

Inventors: Atsushi Umezaki (Kanagawa, JP); Hajime Kimura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,599,998
App. No.
13/025,479
Granted
Dec 3, 2013
Kind
B2
Abstract

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

Claims (74)

1. A semiconductor device comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line,

wherein each channel region of the second transistor and the third transistor includes an oxide semiconductor, and

wherein a ratio of a channel width to a channel length of the second transistor is 0.1 times or more and less than 1 time a ratio of a channel width to a channel length of the third transistor.

2. The semiconductor device according to claim 1 , wherein each off-state current of at least the second transistor and the third transistor is 1 aA/mm or less.

3. A display device comprising the semiconductor device according to claim 1 .

4. The semiconductor device according to claim 1 , wherein a channel region of the third transistor includes an oxide semiconductor.

5. A driving method of a semiconductor device comprising a first transistor, a second transistor, and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line,

wherein each channel region of the second transistor and the third transistor comprises an oxide semiconductor, and

wherein a ratio of a channel width to a channel length of the second transistor is 0.1 times or more and less than 1 time a ratio of a channel width to a channel length of the third transistor,

the driving method comprising the steps of:

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a first period;

turning on the third transistor, thereby establishing electrical continuity between the third line and a gate of the first transistor in the first period;

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a second period;

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a third period;

turning on the second transistor, thereby establishing electrical continuity between the second line and the gate of the first transistor in the third period; and

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a fourth period.

6. The driving method of a semiconductor device according to claim 5 , wherein each off-state current of at least the second transistor and the third transistor is 1 aA/mm or less.

7. The driving method of a semiconductor device according to claim 5 , wherein a ratio of a channel width to a channel length of the first transistor is twice or more and less than 20 times a ratio of a channel width to a channel length of the third transistor.

8. The driving method of a semiconductor device according to claim 5 , the semiconductor device further comprising:

a fourth transistor; and

a fifth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth line, the other of the source and the drain of the fourth transistor is electrically connected to the second line, and

wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a fifth line,

the driving method further comprising the steps of:

turning off the fourth transistor, thereby breaking electrical continuity between the fourth line and the second line in the first to third periods,

turning off the fifth transistor, thereby breaking electrical continuity between the fourth line and the gate of the first transistor in the first to third periods,

turning off the fourth transistor, thereby breaking electrical continuity between the fourth line and the second line in the fourth period, and

turning off the fifth transistor, thereby breaking electrical continuity between the fourth line and the gate of the first transistor in the fourth period.

9. The driving method of a semiconductor device according to claim 8 , the semiconductor device further comprising a sixth transistor wherein one of a source and a drain of the sixth transistor is electrically connected to the fourth line, the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,

the driving method further comprising the step of:

turning on the sixth transistor, thereby establishing electrical continuity between the fourth line and the gate of the fourth transistor in the first to fourth periods.

10. The driving method of a semiconductor device according to claim 5 , further comprising the steps of:

turning off the second transistor, thereby breaking electrical continuity between the second line and the gate of the first transistor in the first period;

turning off the third transistor, thereby breaking electrical continuity between the third line and the gate of the first transistor in the second period;

turning off the second transistor, thereby breaking electrical continuity between the second line and the gate of the first transistor in the second period;

turning off the third transistor, thereby breaking electrical continuity between the third line and the gate of the first transistor in the third period;

turning off the third transistor, thereby breaking electrical continuity between the third line and the gate of the first transistor in the fourth period; and

turning off the second transistor, thereby breaking electrical continuity between the second line and the gate of the first transistor in the fourth period.

11. A semiconductor device comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line,

wherein each channel region of the second transistor and the third transistor includes an oxide semiconductor, and

wherein a ratio of a channel width to a channel length of the first transistor is twice or more and less than 20 times a ratio of a channel width to a channel length of the third transistor.

12. The semiconductor device according to claim 11 , wherein each off-state current of at least the second transistor and the third transistor is 1 aA/mm or less.

13. A display device comprising the semiconductor device according to claim 11 .

14. The semiconductor device according to claim 11 , wherein a channel region of the third transistor includes an oxide semiconductor.

15. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line,

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth line, the other of the source and the drain of the fourth transistor is electrically connected to the second line,

wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a fifth line, and

wherein each channel region of the second transistor and the third transistor includes an oxide semiconductor, a sixth transistor, and a capacitor, wherein one of a source and a drain of the sixth transistor is electrically connected to the fourth line, the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor, and a gate of the sixth transistor is electrically connected to the gate of the first transistor, and wherein a first electrode of the capacitor is electrically connected to the first line, and a second electrode of the capacitor is electrically connected to the gate of the fourth transistor.

16. The semiconductor device according to claim 15 , wherein each off-state current of at least the second transistor and the third transistor is 1 aA/mm or less.

17. A display device comprising the semiconductor device according to claim 15 .

18. The semiconductor device according to claim 15 , wherein a channel region of the third transistor includes an oxide semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2011
From: UMEZAKI, ATSUSHI; KIMURA, HAJIME
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025807/0769 →
Priority Claims (1)
JP 2010-036902 · Feb 23, 2010 · national
Continuity (1)
Related Publication 20110204928A1 · Aug 25, 2011