IP Library Granted Patent US 8,873,638
Granted Patent B2
US 8,873,638 · App. 13/025,611 · Granted Oct 28, 2014

Method and apparatus for providing multi-threaded video decoding

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Quick Facts
Patent No.
US 8,873,638
App. No.
13/025,611
Granted
Oct 28, 2014
Kind
B2
Abstract

An apparatus for enabling provision of multi-thread video decoding may include at least one processor and at least one memory including computer program code. The at least one memory and the computer program code may be configured, with the processor, to cause the apparatus to perform at least assigning decoding of a respective video frame to a corresponding thread for each core processor of a multi-core processor in which each respective video frame is divided into macroblock rows, resolving dependencies for each respective video frame at a macroblock row level, and providing synchronization for video decoding of each corresponding thread at the macroblock row level. A corresponding method and computer program product are also provided.

Claims (40)

1. An apparatus comprising:

at least one processor; and

at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to at least perform:

assigning decoding of a respective video frame to a corresponding thread for each core processor of a multi-core processor, each respective video frame being divided into macroblock rows;

resolving dependencies for the each respective video frame at a macroblock row level; and

providing synchronization for video decoding of each corresponding thread at the macroblock row level; where

resolving dependencies comprises during decoding limiting a predicted motion vector in advance based on a maximum motion vector of a prior row; and

where synchronization is provided by limiting a maximum lag between decoding successive frames based on frame resolution and cache size of a cache having shared access among each core processor of the multi-core processor.

2. The apparatus of claim 1 , wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus at least to further perform:

resolving dependencies by determining an availability of a decoded macroblock row in a reference frame.

3. The apparatus of claim 2 , wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus at least to further perform:

providing synchronization by performing synchronization based on the availability of the decoded macroblock row in the reference frame.

4. The apparatus of claim 1 , wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus at least to further perform:

resolving dependencies by determining whether a position pointed to in a reference frame has been decoded prior to decoding a macroblock row, the position pointed to being determined by adding current row position and a maximum vertical motion vector range.

5. The apparatus of claim 1 , wherein the at least one memory and computer program code are configured to, with the at least one processor, cause the apparatus at least to further perform:

providing synchronization by updating a probability table for a frame after a probability table for a previous frame has been updated for a video decoder that uses a context adaptive decoding process.

6. A method comprising:

assigning decoding of a respective video frame to a corresponding thread for each core processor of a multi-core processor, each respective video frame being divided into macroblock rows;

resolving dependencies for each respective video frame at a macroblock row level;

providing synchronization for video decoding of each corresponding thread at the macroblock row level; where

resolving dependencies comprises during decoding limiting a predicted motion vector in advance based on a maximum motion vector of a prior row; and

where synchronization is provided by limiting a maximum lag between decoding successive frames based on frame resolution and cache size of a cache having shared access among each core processor of the multi-core processor.

7. The method of claim 6 , wherein resolving dependencies comprises determining an availability of a decoded macroblock row in a reference frame.

8. The method of claim 7 , wherein providing synchronization comprises performing synchronization based on the availability of the decoded macroblock row in the reference frame.

9. The method of claim 6 , wherein resolving dependencies comprises determining whether a position pointed to in a reference frame has been decoded prior to decoding a macroblock row, the position pointed to being determined by adding current row position and a maximum vertical motion vector range.

10. The method of claim 6 , wherein providing synchronization comprises updating a probability table for a frame after a probability table for a previous frame has been updated for a video decoder that uses a context adaptive decoding process.

11. A computer program product comprising at least one non-transitory computer-readable storage medium having computer-executable program code instructions stored thereon, the computer-executable program code instructions when executed by an apparatus cause the apparatus to perform:

assigning decoding of a respective video frame to a corresponding thread for each core processor of a multi-core processor, each respective video frame being divided into macroblock rows;

resolving dependencies for each respective video frame at a macroblock row level; and

providing synchronization for video decoding of each corresponding thread at the macroblock row level; where

resolving dependencies comprises during decoding limiting a predicted motion vector in advance based on a maximum motion vector of a prior row; and

where synchronization is provided by limiting a maximum lag between decoding successive frames based on frame resolution and cache size of a cache having shared access among each core processor of the multi-core processor.

12. The computer program product of claim 11 , wherein program code instructions cause the apparatus at least to further perform:

determining an availability of a decoded macroblock row in a reference frame.

13. The computer program product of claim 12 , wherein program code instructions cause the apparatus at least to further perform:

synchronizing based on the availability of the decoded macroblock row in the reference frame.

14. The computer program product of claim 11 , wherein program code instructions cause the apparatus at least to further perform:

determining whether a position pointed to in a reference frame has been decoded prior to decoding a macroblock row, the position pointed to being determined by adding current row position and a maximum vertical motion vector range.

15. The computer program product of claim 11 , wherein program code instructions cause the apparatus at least to further perform:

updating a probability table for a frame after a probability table for a previous frame has been updated for a video decoder that uses a context adaptive decoding process, or limiting a maximum lag between decoding successive frames based on frame resolution and cache size of a cache having shared access among each core processor of the multi-core processor.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2021
From: PROVENANCE ASSET GROUP LLC
To: RPX CORPORATION
Reel/Frame 059352/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 30, 2021
From: NOKIA US HOLDINGS INC.
To: PROVENANCE ASSET GROUP HOLDINGS LLC; PROVENANCE ASSET GROUP LLC
Reel/Frame 058363/0723 →
RELEASE OF SECURITY INTEREST Recorded Nov 30, 2021
From: CORTLAND CAPITAL MARKETS SERVICES LLC
To: PROVENANCE ASSET GROUP HOLDINGS LLC; PROVENANCE ASSET GROUP LLC
Reel/Frame 058983/0104 →
ASSIGNMENT AND ASSUMPTION AGREEMENT Recorded Feb 14, 2019
From: NOKIA USA INC.
To: NOKIA US HOLDINGS INC.
Reel/Frame 048370/0682 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2017
From: NOKIA TECHNOLOGIES OY; NOKIA SOLUTIONS AND NETWORKS BV; ALCATEL LUCENT SAS
To: PROVENANCE ASSET GROUP LLC
Reel/Frame 043877/0001 →
SECURITY INTEREST Recorded Sep 13, 2017
From: PROVENANCE ASSET GROUP HOLDINGS, LLC; PROVENANCE ASSET GROUP LLC
To: NOKIA USA INC.
Reel/Frame 043879/0001 →
SECURITY INTEREST Recorded Sep 13, 2017
From: PROVENANCE ASSET GROUP HOLDINGS, LLC; PROVENANCE ASSET GROUP, LLC
To: CORTLAND CAPITAL MARKET SERVICES, LLC
Reel/Frame 043967/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: NOKIA CORPORATION
To: NOKIA TECHNOLOGIES OY
Reel/Frame 035501/0191 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2011
From: KUMAR, CHIRANTAN; KIMIDI, SUDHAKARA RAO
To: NOKIA CORPORATION
Reel/Frame 025796/0411 →