Integrated circuit comprising a FRAM memory and method for granting read-access to a FRAM memory

1. An integrated circuit comprising:

a Ferroelectric Random Access Memory (FRAM);

an integrated capacitor connected between a power supply for said FRAM memory and ground, the integrated capacitor having a capacitance sufficient to store a charge necessary for a complete read-and-write-back cycle of said FRAM memory; and

a switch connected between the power supply for said FRAM memory and said integrated capacitor, said switch operable to selectively connect or disconnect said integrated capacitor from the power supply.

2. The integrated circuit of claim 1 , further comprising:

a charge detector connected to the integrated capacitor, said charge detector outputting a charge completed signal if said integrated capacitor is sufficiently charged for a complete read-and-write-back cycle of said FRAM.

3. The integrated circuit of claim 1 , further comprising:

an access controller connected to said switch, said charge detector and an read-access input of said FRAM, said access controller supplying a signal to the read-access input of said FRAM permitting read-access to said FRAM memory only if said charge detector outputs said charge completed signal indicating the charge detected on said integrated capacitor is sufficient for a complete read-and-write-back cycle of said FRAM memory and said switch has disconnected said integrated capacitor from the power supply.

4. The integrated circuit of claim 3 , wherein:

said access controller is implemented with Muller-C-elements forming an asynchronous state machine.

5. An integrated circuit comprising:

a Ferroelectric Random Access Memory (FRAM) having a power input, an access grant input and a read-and-write-back cycle complete output;

a first integrated capacitor having a first terminal and second terminal connected to ground, the first integrated capacitor having a capacitance sufficient to store a charge necessary for a complete read-and-write-back cycle of said FRAM memory;

a first charge detector connected to said first integrated capacitor, said first charge detector outputting a first charge completed signal if said first integrated capacitor is sufficiently charged for a complete read-and-write-back cycle of said FRAM;

a first set of switches connected to a power supply, said power input of said FRAM and said first terminal of said first integrated capacitor, said first set of switches alternately connecting said first terminal of said first integrated capacitor to the power supply and to said power input of said FRAM;

a second integrated capacitor having first and second terminals, the second integrated capacitor having a capacitance sufficient to store a charge necessary for a complete read-and-write-back cycle of said FRAM memory;

a second charge detector connected to said second integrated capacitor, said second charge detector outputting a second charge completed signal if said second integrated capacitor is sufficiently charged for a complete read-and-write-back cycle of said FRAM;

a second set of switches connected to a power supply, said power input of said FRAM and said first terminal of said second integrated capacitor, said second set of switches alternately connecting said first terminal of said second integrated capacitor to said power input of said FRAM and to the power supply;

an access controller connected to said FRAM, said first and second sets of switches and said first and second charge detectors and receiving an access request signal, said access controller operable upon receipt of an access request signal to

control a first of said first and second switches to connect a corresponding one of said first or second integrated capacitor to said power input of said FRAM,

control a second of said first and second switches to connect a corresponding one of said first or second integrated capacitor to said power supply,

control said first of said first and second switches to disconnect said corresponding one of said first or second integrated capacitor from said power input of said FRAM upon receipt of said read-and-write-back cycle complete output from said FRAM, and

control a second of said first and second switches to disconnect a corresponding one of said first or second integrated capacitor from said power supply upon receipt of a charge complete signal from a corresponding one of said first and second charge detectors.

6. A method for granting read-access to a Ferroelectric Random Access Memory (FRAM) on an integrated circuit, comprising the steps of:

supplying the FRAM memory by a capacitor internal to the integrated circuit;

upon receiving a request for a read-access to the FRAM memory, detecting whether the capacitor internal to the integrated circuit stores sufficient charge for a complete read-and-write-back cycle of the FRAM memory and disconnecting the capacitor internal to the integrated circuit from the power supply; and

granting read-access to the FRAM memory only if the capacitor internal to the integrated circuit stores sufficient charge and the capacitor internal to the integrated circuit is disconnected from the power supply.

7. The method of claim 6 , further comprising the step of:

charging the capacitor internal to the integrated circuit only after receiving the request for a read-access to the FRAM memory.

8. The method of claim 6 , further comprising the step of:

charging the capacitor internal to the integrated circuit after a complete read-and-write-back cycle of the FRAM memory.

9. The method of claim 6 , further comprising the step of:

connecting the capacitor internal to the integrated circuit to the power supply only during charging.

10. A method for granting read-access to a Ferroelectric Random Access Memory (FRAM) on an integrated circuit, comprising the steps of:

upon receiving a request for a read-access to the FRAM memory alternately (1) supplying the FRAM memory by a first capacitor internal to the integrated circuit and charging a second capacitor internal to the integrated circuit and (2) supplying the FRAM memory by the second capacitor internal to the integrated circuit and charging the first capacitor internal to the integrated circuit;

ceasing supply of the FRAM memory from one of the first and second capacitor internal to the integrated circuit upon completion of a FRAM read-and-write-back cycle; and

ceasing charging one of the first and second capacitor internal to the integrated circuit upon detecting the corresponding capacitor internal to the integrated circuit stores sufficient charge for a complete read-and-write-back cycle of the FRAM memory.