Granted Patent B1

US 8,390,367 · App. 13/027,504 · Granted Mar 5, 2013

Abstract

Claims (42)

1. A computing device comprising:

digital circuitry; and

a gate speed regulator operable to generate a supply voltage applied to the digital circuitry, the gate speed regulator comprising:

a frequency synthesizer operable to generate a first reference frequency;

a propagation delay oscillator operable to generate a first oscillation frequency in response to the supply voltage, wherein the first oscillation frequency is compared to the first reference frequency to generate a first error signal;

a reference oscillator operable to generate a second reference frequency in response to a reference voltage;

a startup oscillator operable to generate a second oscillation frequency in response to the supply voltage, wherein the second oscillation frequency is compared to the second reference frequency to generate a second error signal; and

an adjustable circuit, responsive to the first and second error signals, for adjusting the supply voltage applied to the digital circuitry.

2. The computing device as recited in claim 1 , wherein:

the adjustable circuit is responsive to the second error signal during a startup interval; and

the adjustable circuit is responsive to the first error signal after the startup interval.

3. The computing device as recited in claim 2 , wherein the startup interval allows the frequency synthesizer to stabilize.

4. The computing device as recited in claim 2 , wherein the reference voltage is greater than the supply voltage during the startup interval.

5. The computing device as recited in claim 4 , wherein:

the reference oscillator comprises a first ring oscillator comprising a first number of inverter elements; and

the startup oscillator comprises a second ring oscillator comprising a second number of inverter elements less than the first number of inverter elements.

6. The computing device as recited in claim 4 , wherein:

the reference oscillator drives a first counter pre-loaded with a first value; and

the startup oscillator drives a second counter pre-loaded with a second value different than the first value.

7. The computing device as recited in claim 2 , wherein the propagation delay oscillator and the startup oscillator share at least one inverter element.

8. The computing device as recited in claim 7 , further comprising configuration circuitry operable to configure a plurality of inverter elements into the startup oscillator during the startup interval and operable to configure the plurality of inverter elements into the propagation delay oscillator after the startup interval.

9. A method of operating a computing device comprising digital circuitry, and a gate speed regulator operable to generate a supply voltage applied to the digital circuitry, the method comprising:

generating a first reference frequency;

generating a first oscillation frequency in response to the supply voltage, wherein the first oscillation frequency represents a propagation delay of the digital circuitry and the first oscillation frequency is compared to the first reference frequency to generate a first error signal;

generating a second reference frequency in response to a reference voltage;

generating a startup oscillation frequency in response to the supply voltage, wherein the startup oscillation frequency is compared to the second reference frequency to generate a second error signal; and

adjusting the supply voltage applied to the digital circuitry in response to the first and second error signals.

10. The method as recited in claim 9 , further comprising:

adjusting the supply voltage in response to the second error signal during a startup interval; and

adjusting the supply voltage in response to the first error signal after the startup interval.

11. The method as recited in claim 10 , wherein the startup interval allows the frequency synthesizer to stabilize.

12. The method as recited in claim 10 , wherein the reference voltage is greater than the supply voltage during the startup interval.

13. The method as recited in claim 12 , wherein:

the second reference frequency is generated by a reference oscillator comprising a first ring oscillator comprising a first number of inverter elements; and

the startup oscillation frequency is generated by a startup oscillator comprises a second ring oscillator comprising a second number of inverter elements less than the first number of inverter elements.

14. The method as recited in claim 12 , further comprising:

generating the second reference frequency using a reference oscillator that drives a first counter pre-loaded with a first value; and

generating the startup oscillation frequency using a startup oscillator that drives a second counter pre-loaded with a second value different than the first value.

15. The method as recited in claim 12 , further comprising:

generating the first oscillation frequency using a propagation delay oscillator; and

generating the startup oscillation frequency using a startup oscillator, wherein the propagation delay oscillator and the startup oscillator share at least one inverter element.

16. The method as recited in claim 15 , further comprising configuring a plurality of inverter elements into the startup oscillator during the startup interval and operable to configure the plurality of inverter elements into the propagation delay oscillator after the startup interval.

Assignments (8)