IP Library Granted Patent US 8,464,106
Granted Patent B2
US 8,464,106 · App. 13/027,597 · Granted Jun 11, 2013

Computer system with backup function and method therefor

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Quick Facts
Patent No.
US 8,464,106
App. No.
13/027,597
Granted
Jun 11, 2013
Kind
B2
Abstract

A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device.

Claims (38)

1. A method for automatic backup of a first solid-state mass storage device of a host system by predetermining a failure of the first solid-state mass storage device, the first solid-state mass storage device comprising a controller and at least one nonvolatile memory device comprising pages that are organized into memory blocks, the method comprising:

assigning at least a first memory block of the memory blocks as wear indicator means and excluding the wear indicator means from use as data storage for the nonvolatile memory device;

using at least a first set of the memory blocks of the nonvolatile memory device as data blocks for data storage whereby data are written to and erased from each of the data blocks in program/erase (P/E) cycles;

collecting information regarding the number of P/E cycles encountered by the data blocks and accessing the information to perform wear leveling on the data blocks;

subjecting the wear indicator means to P/E cycles so that the wear indicator means is subjected to a number of P/E cycles that is greater than the number of P/E cycles encountered by the data blocks;

performing integrity checks of the wear indicator means and monitoring a bit error rate thereof; and

taking corrective action if the bit error rate of the wear indicator means reaches a predetermined threshold, the corrective action comprising connecting the first solid-state mass storage device to a second mass storage device of the host system, and then initiating a data backup procedure comprising copying data stored in the data blocks of the first solid-state mass storage device to the second mass storage device.

2. The method of claim 1 , further comprising assigning at least a second set of the memory blocks of the nonvolatile memory device as over-provisioned memory blocks for the nonvolatile memory device, and excluding the wear indicator means from the over-provisioned memory blocks.

3. The method of claim 1 , wherein the corrective action further comprises suspending operation of the first solid-state mass storage device after completion of the data backup procedure.

4. The method of claim 1 , wherein after completion of the data backup procedure, the corrective action further comprises the host system generating a request to replace the first solid-state mass storage device with a compatible solid-state mass storage device.

5. The method of claim 4 , wherein the corrective action further comprises identifying the data copied from the first solid-state mass storage device with at least one identifier.

6. The method of claim 5 , wherein the identifier comprises an identification of the first solid-state mass storage device.

7. The method of claim 5 , further comprising replacing the first solid-state mass storage device with the compatible solid-state mass storage device, and then using the identifier of the first solid-state mass storage device to enable the compatible solid-state mass storage device to access and recover the backed-up data from the second mass storage device as soon as the compatible solid-state mass storage device is installed.

8. The method of claim 1 , wherein the first solid-state mass storage device is a NAND flash memory device.

9. The method of claim 1 , wherein the second mass storage device is local to the first solid-state mass storage device.

10. The method of claim 1 , wherein the second mass storage device is remote from the first solid-state mass storage device.

11. The method of claim 1 , wherein the second mass storage device is a hard disk drive.

12. The method of claim 1 , wherein the second mass storage device is a solid-state mass storage device.

13. The method of claim 1 , wherein the data backup procedure further comprises copying wear-leveling information obtained from the data blocks and the wear indicator means of the first solid-state mass storage device, the method further comprising performing a statistical analysis of the wear-leveling information to identify a write endurance limitation of the first solid-state mass storage device.

14. The method of claim 13 , further comprising using the statistical analysis to predict failures of other solid-state mass storage devices within the host system.

15. A computer host system adapted to perform an automatic backup of a first solid-state mass storage device to a second mass storage device by predetermining a failure of the first solid-state mass storage device;

the first solid-state mass storage device comprising:

a controller;

at least one nonvolatile memory device comprising pages that are organized into memory blocks, at least a first memory block of the memory blocks assigned as wear indicator means that is excluded from use as data storage for the nonvolatile memory device, and at least a first set of the memory blocks of the nonvolatile memory device used as data blocks for data storage whereby data are written to and erased from each of the data blocks in program/erase (P/E) cycles;

means for performing wear leveling to maintain substantially the same level of usage across the data blocks;

means for subjecting the wear indicator means to P/E cycles so that the wear indicator means is subjected to a number of P/E cycles that is greater than the number of P/E cycles encountered by the data blocks; and

means for performing integrity checks of the wear indicator means and monitoring a bit error rate thereof;

the computer host system comprising means for taking corrective action if the bit error rate of the wear indicator means reaches a predetermined threshold, the corrective action means operating to connect the first solid-state mass storage device to the second mass storage device and then initiate a data backup procedure that comprises copying to the second mass storage device all data stored in the data blocks of the first solid-state mass storage device.

16. The computer host system of claim 15 , wherein the first solid-state mass storage device further comprises at least a second set of the memory blocks of the nonvolatile memory device assigned as over-provisioned memory blocks for the nonvolatile memory device, and the wear indicator means are excluded from the over-provisioned memory blocks.

17. The computer host system of claim 15 , wherein the corrective action means further operates to suspend operation of the first solid-state mass storage device after completion of the data backup procedure.

18. The computer host system of claim 15 , wherein the corrective action means further operates to generate a request to replace the first solid-state mass storage device with a compatible solid-state mass storage device after completion of the data backup procedure.

19. The computer host system of claim 15 , wherein the corrective action means further operates to identify the data copied from the first solid-state mass storage device with at least one identifier.

20. The computer host system of claim 15 , wherein the first solid-state mass storage device is a NAND flash memory device.

21. The computer host system of claim 15 , wherein the second mass storage device is local to the first solid-state mass storage device.

22. The computer host system of claim 15 , wherein the second mass storage device is remote from the first solid-state mass storage device.

23. The computer host system of claim 15 , wherein the second mass storage device is a hard disk drive.

24. The computer host system of claim 15 , wherein the controller of the first solid-state mass storage device comprises the wear-leveling performing means, the subjecting means, and the integrity check performing means.

25. The computer host system of claim 15 , further comprising wear-leveling information obtained from the data blocks and the wear indicator means of the first solid-state mass storage device and on which statistical analysis can be performed to identify a write endurance limitation of the first solid-state mass storage device.

Assignments (15)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Apr 8, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0284 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Apr 8, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0455 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE AND ATTACH A CORRECTED ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 032365 FRAME 0920. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT EXECUTION DATE IS JANUARY 21, 2014. Recorded Mar 18, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032461/0486 →
CHANGE OF NAME Recorded Feb 27, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 032365/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032365/0920 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2011
From: FILOR, LUTZ; SCHUETTE, FRANZ MICHAEL
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 026032/0330 →