Granted Patent B1

US 8,350,628 · App. 13/027,616 · Granted Jan 8, 2013

Abstract

Claims (25)

1. A computing device comprising:

digital circuitry comprising a critical path circuit; and

a gate speed regulator comprising:

a ring oscillator operable to generate an oscillation frequency;

dither circuitry operable to periodically adjust a number of inverter elements in the ring oscillator over a number of cycles in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit;

a comparator operable to compare the oscillation frequency to a reference frequency to generate an error signal; and

an adjustable circuit, responsive to the error signal, for adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry.

2. The computing device as recited in claim 1 , wherein the dither circuitry is operable to adjust the average propagation delay of the ring oscillator to substantially match a multiple of the propagation delay of the critical path circuit.

3. The computing device as recited in claim 1 , wherein the dither circuitry is operable to adjust the average propagation delay of the ring oscillator to substantially match a divisor of the propagation delay of the critical path circuit.

4. The computing device as recited in claim 1 , wherein the dither circuitry comprises a multiplexer operable to selectively remove at least one inverter element from the ring oscillator.

5. The computing device as recited in claim 4 , wherein the multiplexer is operable to selectively remove two inverter elements from the ring oscillator.

6. The computing device as recited in claim 4 , wherein the dither circuitry periodically configures the multiplexer.

7. The computing device as recited in claim 6 , wherein the dither circuitry comprises a counter for periodically configuring the multiplexer.

8. The computing device as recited in claim 7 , wherein the oscillation frequency is operable to drive the counter.

9. A method of operating a computing device comprising digital circuitry comprising a critical path circuit, the method comprising:

using a ring oscillator to generate an oscillation frequency;

periodically adjusting a number of inverter elements in the ring oscillator over a number of cycles in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit;

comparing the oscillation frequency to a reference frequency to generate an error signal; and

adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry in response to the error signal.

10. The method as recited in claim 9 , further comprising adjusting the average propagation delay of the ring oscillator to substantially match a multiple of the propagation delay of the critical path circuit.

11. The method as recited in claim 9 , further comprising adjusting the average propagation delay of the ring oscillator to substantially match a divisor of the propagation delay of the critical path circuit.

12. The method as recited in claim 9 , further comprising removing at least one inverter element from the ring oscillator.

13. The method as recited in claim 12 , further comprising periodically removing two inverter elements from the ring oscillator.

14. The method as recited in claim 12 , further comprising using a counter to periodically remove at least one inverter element from the ring oscillator.

15. The method as recited in claim 14 , further comprising driving the counter with the oscillation frequency.

Assignments (8)