Execute only access rights on a Von Neuman architectures
View Patent ↗A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected area to access data in the protected area while preventing instructions fetched from outside the protected area from accessing data in the protected area.
1. A method comprising:
receiving one or more signals indicating a memory access;
reading a current address;
determining that the current address is within a protected area of a memory map, the protected area defined by a base address, a limit address, and a non-zero offset;
in response to determining that the current address is within the protected area of the memory map, setting an access flag;
determining that the one or more signals indicate a fetch memory access and that the fetch memory access is not within the protected area of the memory;
in response to determining that the one or more signals indicate a fetch memory access and that the fetch memory access is not within the protected area of the memory, clearing a protected fetch flag;
determining that the one or more signals indicate a data memory access, that the access flag is set, and that the protected fetch flag is cleared; and
in response to determining that the one or more signals indicate a data memory access, that the access flag is set, and that the protected fetch flag is cleared, aborting the data memory access.
2. The method of claim 1 , further comprising:
receiving one or more different signals indicating a memory access;
determining that the one or more different signals indicate a data memory access;
determining that the access flag is cleared or that the protected fetch flag is set; and
in response to determining that the access flag is cleared or that the protected fetch flag is set, allowing the data memory access.
3. The method of claim 1 , wherein determining that the current address is within a protected area of the memory map further comprises:
determining that the current address is greater than or equal to the sum of the base address and the non-zero offset and that the current address is less than or equal to the limit address.
4. The method of claim 1 , wherein aborting the data memory access further comprises:
setting an abort flag to abort the data memory access.
5. The method of claim 1 , wherein determining that the one or more signals indicate a data memory access further comprises:
determining that the one or more signals indicate a read data memory access.
6. The method of claim 1 , wherein determining that the one or more signals indicate a data memory access further comprises:
determining that the one or more signals indicate a write data memory access.
7. The method of claim 1 , wherein the base address and the limit address are fixed.
8. The method of claim 1 , wherein the base address and the limit address are programmable.
9. The method of claim 1 , wherein:
the memory map corresponds to a memory array coupled to a processor; and
the non-zero offset is equal to a number of instruction pipeline stages of the processor minus one.
10. The method of claim 9 , wherein the processor has a Von Neumann architecture.
11. The method of claim 1 , wherein determining that the current address is within a protected area of a memory map further comprises:
determining that the current address is within one of a plurality of protected areas of the memory map, each protected area defined by a respective base address, a respective limit address, and the non-zero offset.