Double transformer balun for maximum power amplifier power
View Patent ↗Double transformer balun for maximum PA (Power Amplifier) power. A novel approach is presented herein by which conversion from a differential signal to single-ended signal may be achieved using a double transformer balun design. The secondary coils of the double transformer balun also operate as a choke for the PA supply voltage. The secondary coils can operate as an RF (Radio Frequency) trap or choke to keep any AC (Alternating Current) signal components and to pass any DC (Direct Current) components. By using a double transformer balun design, relatively thinner tracks may be employed thereby ensuring a high degree of electromagnetic coupling efficiency and high performance. Also, these relatively thinner tracks consume a relatively small amount of space on the die. The double transformer balun design also includes a matching Z (impedance) block that is operable to match the Z of an antenna or line that the PA is driving.
1. An apparatus, comprising:
a double transformer including a first transformer, having a first primary winding and a first secondary winding, and a second transformer, having a second primary winding and a second secondary winding, wherein:
a first end of the first secondary winding and a first end of the second secondary winding connected for receiving a first leg of a differential signal;
a second end of the first secondary winding and a second end of the second secondary winding connected for receiving a second leg of the differential signal;
a first end of the first primary winding and a first end of the second primary winding connected for outputting a single-ended signal; and
a second end of the first primary winding and a second end of the second primary winding grounded.
2. The apparatus of claim 1 , wherein:
a first center tap of the first secondary winding and a second center tap of the second secondary winding connected to a power supply.
3. The apparatus of claim 1 , wherein:
the single-ended signal being generated within the double transformer based on the differential signal.
4. The apparatus of claim 1 , further comprising:
an impedance having an input for receiving the single-ended signal from the double transformer and having an output for providing an off-chip single-ended signal to at least one of an antenna and a line; and wherein:
the impedance effectuating impedance matching with the at least one of an antenna and a line.
5. The apparatus of claim 4 , wherein:
the impedance including a capacitor having a capacitive-reactance for substantially canceling an inductive-reactance associated with at least one of the antenna and the line at a predetermined operating frequency.
6. The apparatus of claim 1 , wherein:
the double transformer implemented within an integrated circuit.
7. The apparatus of claim 1 , further comprising:
a power amplifier (PA) core for providing the differential signal to the double transformer;
an impedance having an input for receiving the single-ended signal from the double transformer and having an output for providing an off-chip single-ended signal to at least one of an antenna and a line; and wherein:
the impedance effectuating impedance matching with the at least one of an antenna and a line;
the PA, the double transformer, and the impedance implemented within an integrated circuit.
8. The apparatus of claim 1 , wherein:
windings of each of the first transformer and the second transformer of the double transformer implemented on an integrated circuit using tracks generated by a CMOS (Complementary Metal Oxide Semiconductor) process of approximately 12 μm (micro-meter) thickness.
9. The apparatus of claim 1 , wherein:
each of the first secondary winding and the second secondary winding operative as an RF (Radio Frequency) choke for substantially blocking any AC (Alternating Current) signal component for the differential signal.
10. The apparatus of claim 1 , wherein:
each of the first primary winding and the second primary winding operative as an RF (Radio Frequency) choke for substantially blocking any AC (Alternating Current) signal component for the on-chip single-ended signal.
11. The apparatus of claim 1 , wherein:
the apparatus being a communication device operative in accordance with at least one wireless communication standard or protocol.
12. An apparatus, comprising:
a power amplifier (PA) core for providing a differential signal;
a double transformer including a first transformer, having a first primary winding and a first secondary winding, and a second transformer, having a second primary winding and a second secondary winding, wherein:
a first end of the first secondary winding and a first end of the second secondary winding connected for receiving a first leg of the differential signal;
a second end of the first secondary winding and a second end of the second secondary winding connected for receiving a second leg of the differential signal;
a first end of the first primary winding and a first end of the second primary winding connected for outputting a single-ended signal;
a second end of the first primary winding and a second end of the second primary winding grounded; and
a first center tap of the first secondary winding and a second center tap of the second secondary winding connected to a power supply; and
an impedance having an input for receiving the single-ended signal from the double transformer and having an output for providing an off-chip single-ended signal to at least one of an antenna and a line.
13. The apparatus of claim 12 , wherein:
the impedance effectuating impedance matching with the at least one of an antenna and a line; and
the impedance including a capacitor having a capacitive-reactance for substantially canceling an inductive-reactance associated with at least one of the antenna and the line at a predetermined operating frequency.
14. The apparatus of claim 12 , wherein:
the PA, the double transformer, and the impedance implemented within an integrated circuit.
15. The apparatus of claim 12 , wherein:
windings of each of the first transformer and the second transformer of the double transformer implemented on an integrated circuit using tracks generated by a CMOS (Complementary Metal Oxide Semiconductor) process of approximately 12 μm (micro-meter) thickness.
16. The apparatus of claim 12 , wherein:
the apparatus being a communication device operative in accordance with at least one wireless communication standard or protocol.
17. A method for operating a communication device, the method comprising:
employing a double transformer for receiving a differential signal, wherein the double transformer including a first transformer, having a first primary winding and a first secondary winding, and a second transformer, having a second primary winding and a second secondary winding, including:
at a first end of the first secondary winding connected to a first end of the second secondary winding, receiving a first leg of the differential signal;
at a second end of the first secondary winding connected to a second end of the second secondary winding, receiving a second leg of the differential signal;
from a first end of the first primary winding connected to a first end of the second primary winding, outputting a single-ended signal as a second end of the first primary winding and a second end of the second primary winding grounded.
18. The method of claim 17 , further comprising:
receiving the differential signal from a power amplifier (PA) core;
employing an impedance having an input for receiving the single-ended signal from the double transformer and having an output for providing an off-chip single-ended signal to at least one of an antenna and a line; and wherein:
the impedance effectuating impedance matching with the at least one of an antenna and a line;
the PA, the double transformer, and the impedance implemented within an integrated circuit of the communication device.
19. The method of claim 17 , wherein:
windings of each of the first transformer and the second transformer of the double transformer implemented on an integrated circuit using tracks generated by a CMOS (Complementary Metal Oxide Semiconductor) process of approximately 12 μm (micro-meter) thickness.
20. The method of claim 17 , wherein:
the communication device operative in accordance with at least one wireless communication standard or protocol.