Method and electronic device for a simplified integration of high precision thinfilm resistors
View Patent ↗The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.
1. A method of manufacturing an integrated circuit, the method comprising:
depositing and structuring an electrically resistive layer of a material for serving as a thin film resistor (TFR),
depositing a first electrically insulating layer on the electrically resistive layer of the TFR,
depositing a first conductive layer of an electrically conductive material,
leaving an area without the first conductive layer overlapping the electrically resistive layer of the TFR,
depositing a second electrically insulating layer on top of the first conductive layer,
etching a first VIA opening through the second insulating layer, the area without the first conductive layer adjacent to the first conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR, and
depositing a conductive material in the first VIA opening to form a first via that directly electrically connects the first conductive layer and the electrically resistive layer of the TFR.
2. The method according to claim 1 , further comprising etching a second VIA opening through the second insulating layer for connecting the conductive layer and using the same single mask for the first VIA opening and the second VIA opening.
3. The method according to claim 2 , further comprising the step of forming a second conductive layer over the second insulating layer wherein the first VIA connects the second conductive layer to the resistive layer of the TFR and the second VIA opening connects the second conductive layer to the first conductive layer.
4. The method according to claim 1 , wherein a width of the first VIA opening adjacent to the electrically conductive layer is greater than a width of the first VIA opening within the electrically conductive layer.
5. The method according to claim 1 , further comprising depositing an etch stop layer on top of the first conductive layer.
6. A method of manufacturing an integrated circuit, the method comprising:
depositing and structuring an electrically resistive layer of a material for serving as a thin film resistor (TFR),
depositing a first electrically insulating layer on the electrically resistive layer of the TFR,
depositing a first conductive layer of an electrically conductive material,
leaving an area without the first conductive layer overlapping the electrically resistive layer of the TFR,
depositing a second electrically insulating layer on top of the first conductive layer,
etching a first VIA opening through the second insulating layer, the area without the first conductive layer adjacent to the first conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR, and
depositing a conductive material in the first VIA opening to form a first via that electrically connects the first conductive layer and the electrically resistive layer of the TFR, wherein a diameter of the first VIA is greater than a width of the electrically resistive layer of the TFR.
7. A method of manufacturing an integrated circuit, the method comprising:
forming a first metal interconnect layer METn−1;
forming a first insulating layer over METn−1;
forming a resistive layer of a thin film resistor TFR embedded within the first insulating layer;
forming a second metal interconnect layer METn over the first insulating layer, the second metal interconnect layer METn having a slot without conductive material overlying a portion of the TFR;
forming a second insulating layer over METn;
forming a masking layer over the second insulating layer;
using said masking layer, forming both a first VIA opening and a second VIA opening, wherein the first VIA opening extends through the second insulating layer, the slot without conductive material in METn, and the first insulating layer to the resistive layer of TFR and the second VIA opening extends through the second insulating layer to METn;
filling the first VIA opening and the second VIA opening with a conductive material to form a first VIA and a second VIA, respectively; and
forming a third metal interconnect layer METn+1, wherein the first VIA connects METn+1 to the resistive layer of TFR through said slot and the second VIA connects METn+1 to METn, and wherein the first VIA is directly connected to METn within said slot.