Selective delay of data receipt in stochastic computation

1. An integrated circuit for stochastic computation, said integrated circuit comprising:

circuitry forming a plurality of processing nodes, including a first processing node and a second processing node, each of said processing nodes configured to process an outcome stream having a plurality of outcomes, each of said plurality of outcomes in said outcome stream being in one of a plurality of states, wherein an outcome from said outcome stream is in a particular state with a particular probability;

circuitry forming communication links configured to transmit outcome streams between pairs of said plurality of processing nodes; and

circuitry forming a delay module on each of said communication links, said delay module configured to delay outcome streams traversing said communication link by an assigned delay;

wherein said first and second processing nodes are connected by a plurality of data paths, at least one of which comprises a plurality of communication links, each of said data paths connecting the first and second processing nodes and causing an aggregate delay to an outcome stream traversing said data path;

wherein the assigned delays of the communication links traversed by each of said data paths connecting the first and second processing nodes are selected subject to the constraint that no two aggregate delays impose the same delay on an outcome stream.

2. The integrated circuit of claim 1 , wherein the assigned delays of the communication links traversed by each of said data paths connecting the first and second processing nodes are selected to reduce the extent to which outcome streams traversing the plurality of data paths between the first and second processing nodes are correlated with each other.

3. The integrated circuit of claim 1 , wherein each communication link of the plurality of communication links is assigned a color, each color is assigned a delay, and for all processing nodes, no two communication links to said processing node have the same color.

4. The integrated circuit of claim 1 , wherein said plurality of processing nodes and communication links define a sub-graph of a larger graph.

5. The integrated circuit of claim 1 , wherein said delay module is configured to delay an incoming outcome stream by an integer multiple of an interval between adjacent outcomes in said incoming outcome stream.

6. The integrated circuit of claim 1 , wherein processing nodes of said plurality of processing nodes are selected from a group consisting of function nodes and variable nodes, and wherein said plurality of communication links are configured such that no two function nodes are connected to each other by a communication link and no two variable nodes are connected to each other by a communication link.

7. The integrated circuit of claim 1 , wherein said plurality of processing nodes and said communication links define a bipartite graph.

8. The integrated circuit of claim 1 , wherein said plurality of processing nodes are configured to process an outcome stream derived from a Bernoulli process.

9. An article of manufacture having encoded thereon software for executing a stochastic computer, said software comprising instructions that, when executed by a computer, cause the computer to:

define a plurality of processing nodes, including a first processing node and a second processing node, each of said processing nodes configured to process an outcome stream having a plurality of outcomes, each of said plurality of outcomes in said outcome stream being in one of a plurality of states, wherein an outcome from said outcome stream is in a particular state with a particular probability;

define communication links configured to transmit outcome streams between pairs of said processing nodes; and to

wherein said first and second processing nodes are connected by a plurality of data paths, at least one of which comprises a plurality of communication links, each of said data paths connecting the first and second processing nodes and causing an aggregate delay to an outcome stream traversing said data path;

select and assign a delay to each of said communication links for delaying outcome streams traversing said communication link subject to the constraint that no two aggregate delays impose the same delay on an outcome stream.

10. The article of claim 9 , wherein each communication link of the plurality of communication links is assigned a color, each color is assigned a delay, and for all processing nodes, no two communication links to said processing node have the same color.

11. The article of claim 9 , wherein selecting the delays comprises selecting the delays to reduce the extent to which outcome streams traversing the plurality of data paths between the first and second processing nodes are correlated with each other.

12. The article of claim 9 , wherein said plurality of processing nodes and communication links define a sub-graph of a larger graph.

13. The article of claim 9 , wherein said delay module is configured to delay an incoming outcome stream by an integer multiple of an interval between adjacent outcomes in said incoming outcome stream.

14. The article of claim 9 , wherein processing nodes of said plurality of processing nodes are selected from a group consisting of function nodes and variable nodes, and wherein said plurality of communication links are configured such that no two function nodes are connected to each other by a communication link and no two variable nodes are connected to each other by a communication link.

15. The article of claim 9 , wherein said plurality of processing nodes and said communication links define a bipartite graph.

16. The article of claim 9 , wherein said plurality of processing nodes are configured to process an outcome stream derived from a Bernoulli process.

17. An integrated circuit for stochastic computation, said integrated circuit comprising:

circuitry forming a plurality of processing nodes, including a first processing node and a second processing node, each of said processing nodes configured to process an outcome stream having a plurality of outcomes, each of said plurality of outcomes in said outcome stream being in one of a plurality of states, wherein an outcome from said outcome stream is in a particular state with a particular probability;

circuitry forming communication links configured to transmit outcome streams between pairs of said plurality of processing nodes; and

circuitry forming a delay module on each of said communication links, said delay module configured to delay outcome streams traversing said communication link by an assigned delay;

wherein said first and second processing nodes are connected by a plurality of data paths, at least one of which comprises a plurality of communication links, each of said data paths connecting the first and second processing nodes and causing an aggregate delay to an outcome stream traversing said data path; and

wherein no two aggregate delays impose the same delay on an outcome stream, and at least one delay module has a randomly assigned delay.

18. The integrated circuit of claim 17 , wherein the assigned delays of the communication links traversed by each of said data paths connecting the first and second processing nodes are selected to reduce the extent to which outcome streams traversing the plurality of data paths between the first and second processing nodes are correlated with each other.

19. The integrated circuit of claim 17 , wherein said plurality of processing nodes and communication links define a sub-graph of a larger graph.

20. The integrated circuit of claim 17 , wherein said delay module is configured to delay an incoming outcome stream by an integer multiple of an interval between adjacent outcomes in said incoming outcome stream.