RF divider using direct digital synthesis

1. A method of dividing a fixed radio frequency by a frequency divisor to generate an output signal having a desired radio frequency, the method comprising:

successively applying consecutive M-bit sections of a parallel word to an input of a multi-stage multiplexer at a pre-sequencing frequency derived based on the fixed radio frequency and M, said parallel word comprising one or more copies of a frequency dividing bit pattern defining the frequency divisor; and

performing a parallel-to-serial conversion on the M-bit sections of the parallel word in the multi-stage multiplexer based on the fixed radio frequency to generate the output signal having the desired radio frequency, said output signal comprising a serial bit stream of the parallel word.

2. The method of claim 1 wherein performing the parallel-to-serial conversion comprises successively multiplexing groups of bits in the M-bit sections in multiple stages of the multi-stage multiplexer, wherein each stage has a smaller width and a higher frequency than the previous stage, and wherein the last stage of the multi-stage multiplexer outputs the serial bit stream using the fixed radio frequency as a serial bit clock according to the frequency dividing bit pattern to generate the output signal having the desired radio frequency.

3. The method of claim 1 wherein performing the parallel-to-serial conversion comprises successively multiplexing pairs of bits in the M-bit sections in multiple stages of the multi-stage multiplexer, wherein each stage has a smaller width and a higher frequency than the previous stage, wherein the penultimate stage of the multi-stage multiplexer is clocked at half the fixed radio frequency, and wherein the last stage of the multi-stage multiplexer combines the bit streams output by the penultimate stage in a logic gate to generate the output signal having the desired radio frequency.

4. The method of claim 3 further comprising modifying the parallel word with a logic function to generate a modified parallel word, wherein successively applying consecutive M-bit sections of the parallel word comprises successively applying consecutive M-bit sections of the modified parallel word to the input of the multi-stage multiplexer such that the serial bit stream output by the logic gate in the last stage of the multi-stage multiplexer comprises a serial bit stream of the unmodified parallel word.

5. The method of claim 1 wherein the frequency dividing bit pattern comprises P bits and each parallel word comprises N bits, where P≦N, the method further comprising forming the M-bit sections by concatenating M consecutive bits of the N-bit parallel word to form each of the one or more M-bit sections, wherein the concatenated bits wrap around from the end of the N-bit parallel word to the beginning of the N-bit parallel word such that the N-bit parallel word is repeated y times to form x M-bit sections, where x=N/z and y=M/z, and where z=greatest common denominator (N,M).

6. The method of claim 1 wherein the frequency dividing bit pattern comprises P bits, and wherein the frequency divisor is P/2.

7. The method of claim 1 further comprising reducing a second harmonic content of the output signal when the number of 1's in the frequency dividing bit pattern does not equal the number of 0's in the frequency dividing bit pattern.

8. The method of claim 1 wherein the frequency divisor is greater than one, such that the desired radio frequency is less than the fixed radio frequency.

9. The method of claim 1 wherein the divisor is a non-integer.

10. The method of claim 1 wherein the frequency divisor equals one such that the desired radio frequency equals the fixed radio frequency.

11. The method of claim 1 further comprising retiming the output signal to satisfy one or more timing requirements.

12. A radio frequency divider to divide a fixed radio frequency by a frequency divisor to generate an output signal having a desired radio frequency, the radio frequency divider comprising:

a pre-sequencer configured to successively output consecutive M-bit sections of a parallel word at a pre-sequencing frequency derived based on the fixed radio frequency and M, said parallel word comprising one or more copies of a frequency dividing bit pattern defining the frequency divisor; and

a parallel-to-serial converter operatively coupled to an output of the pre-sequencer and configured to perform a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate the output signal having the desired radio frequency, said output signal comprising a serial bit stream of the parallel word.

13. The radio frequency divider of claim 12 wherein a processor coupled to an input of the radio frequency divider is configured to define the parallel word based on the fixed radio frequency and the desired radio frequency.

14. The radio frequency divider of claim 12 wherein the parallel-to-serial converter comprises a multi-stage multiplexer configured to perform the parallel-to-serial conversion by successively multiplexing groups of bits in the M-bit sections applied to an input of the multi-stage multiplexer based on the fixed radio frequency, wherein each stage of the multi-stage multiplexer has a smaller width and a higher frequency than the previous stage, and wherein the last stage of the multi-stage multiplexer outputs the serial bit stream using the fixed radio frequency as a serial bit clock according to the frequency dividing bit pattern to generate the output signal having the desired radio frequency.

15. The radio frequency divider of claim 12 wherein the parallel-to-serial converter comprises a multi-stage multiplexer configured to perform the parallel-to-serial conversion by successively multiplexing pairs of bits in the M-bit sections applied to an input of the multi-stage multiplexer based on the fixed radio frequency, wherein each stage of the multi-stage multiplexer has a smaller width and a higher frequency than the previous stage, wherein the penultimate stage of the multi-stage multiplexer is clocked at half the fixed radio frequency, and wherein the last stage of the multi-stage multiplexer comprises a logic gate to combine the bit streams output by the penultimate stage to generate the output signal having the desired radio frequency.

16. The radio frequency divider of claim 15 wherein a logic function applied to the parallel word generates a modified parallel word, wherein the pre-sequencer is configured to successively output consecutive M-bit sections of the modified parallel word such that the serial bit stream output by the logic gate in the last stage of the multi-stage multiplexer comprises the a serial bit stream of the unmodified parallel word.

17. The radio frequency divider of claim 12 wherein the frequency dividing bit pattern comprises P bits and each parallel word comprises N bits, where P≦N, wherein the pre-sequencer forms the M-bit sections by concatenating M consecutive bits of the N-bit parallel word to form each of the one or more M-bit sections, and wherein the concatenated bits wrap around from the end of the N-bit parallel word to the beginning of the N-bit parallel word such that the N-bit parallel word is repeated y times to form x M-bit sections, where x=N/z and y=M/z, and where z=greatest common denominator (N,M).

18. The radio frequency divider of claim 12 further comprising a chain of AC-coupled inverters configured to reduce a second harmonic content of the output signal when the number of 1's in the frequency dividing bit pattern does not equal the number of 0's in the frequency dividing bit pattern.

19. The radio frequency divider of claim 12 wherein the divisor is a non-integer.

20. The radio frequency divider of claim 12 further comprising a retiming stage operatively connected to an output of the logic gate and configured to retime the output signal to satisfy one or more timing requirements.