ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY AND FABRICATION METHOD THEREOF
An array substrate of a liquid crystal display and a method of fabrication for the same are disclosed. The method of fabrication includes: forming a gate electrode on a first region of a substrate, where the substrate is divided into first and second regions, forming a lower storage electrode, including a transparent conductive material, on the second region of the substrate, and forming a gate insulating layer on the substrate, where the gate insulating layer includes first, second and third gate insulating sub-layers.
1 . A method of fabrication of an array substrate of a liquid crystal display, comprising:
forming a gate electrode on a first region of a substrate, wherein the substrate is divided into first and second regions;
forming a lower storage electrode, comprising a transparent conductive material, on the second region of the substrate; and
forming a gate insulating layer on the substrate;
wherein the gate insulating layer comprises first, second and third gate insulating sub-layers.
2 . The method of fabrication of claim 1 , further comprising:
forming a semiconductor layer in a region overlapping the gate electrode;
forming a source electrode and a drain electrode, configured to be electrically connected to the semiconductor layer; and
forming a pixel electrode in a region overlapping the lower storage electrode and electrically connected to the drain electrode.
3 . The method of fabrication of claim 1 , wherein the first, second and third gate insulating sub-layers are formed of a same material and by application of different deposition rates and flows of gases during a deposition process.
4 . The method of fabrication of claim 3 , wherein a deposition rate applied to the first gate insulating sub-layer is substantially the same as a deposition rate applied to the third gate insulating sub-layers and is different than a deposition rate applied to the second gate insulating sub-layer.
5 . The method of fabrication of claim 4 , wherein the deposition rate applied to the first and third gate insulating sub-layers is lower than the deposition rate applied to the second gate insulating sub-layer.
6 . The method of fabrication of claim 3 , wherein a flow of reduction reaction gas used in the deposition process of the first and third gate insulating sub-layers is lower than a flow of a reduction reaction gas used in the deposition process of the second gate insulating sub-layer.
7 . The method of fabrication of claim 6 , wherein the reduction reaction gas comprises at least one of NH 3 and SiH 4 .
8 . The method of fabrication of claim 6 , wherein the first gate insulating sub-layer is deposited by a flow of SiH 4 gas lower than the flow of gas used to deposit the third gate insulating sub-layer.
9 . The method of fabrication of claim 2 , wherein the lower storage electrode and the pixel electrode are formed with at least one of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
10 . The method of fabrication of claim 1 , further comprising forming a contact electrode formed of the same material as the material of the gate electrode in regions corresponding with the lower storage electrodes.
11 . An array substrate of a liquid crystal display, comprising;
a substrate divided into a plurality of first regions and second regions;
a plurality of gate electrodes formed on the first regions of the substrate;
a lower storage electrode formed on the second regions of the substrate and made of a transparent conductive material;
a gate insulating layer formed over the substrate;
a semiconductor layer formed in a region corresponding with the gate electrodes;
a plurality of source electrodes and a plurality of drain electrodes electrically connected to the semiconductor layer; and
a pixel electrode electrically connected to the drain electrodes and formed on regions corresponding with the lower storage electrodes;
wherein the gate insulating layer has a tiered structure comprising first, second and third gate insulating sub-layers.
12 . The array substrate of claim 11 , wherein the first, second and third gate insulating sub-layers are made of a same material and are formed by application of different deposition rates and flow of gases during a deposition process.
13 . The array substrate of claim 11 , wherein the lower storage electrodes and the pixel electrodes are formed with one of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
14 . The array substrate of claim 11 , further comprising contact electrodes made of the same material as the material of the gate electrodes, and formed in regions corresponding with the lower storage electrodes.
15 . An array substrate of a liquid crystal display, comprising;
a substrate;
a plurality of gate electrodes formed on the substrate of a first material;
a lower storage electrode formed on the substrate and made of a transparent conductive material;
a gate insulating layer formed over the substrate, wherein the gate insulating layer has a tiered structure comprising first, second and third gate insulating sub-layers, wherein the sub-layers are made of a same material;
a semiconductor layer formed in a region corresponding with the gate electrodes;
a plurality of source electrodes and a plurality of drain electrodes electrically connected to the semiconductor layer; and
a pixel electrode electrically connected to the drain electrodes and formed on regions corresponding with the lower storage electrodes; and
a plurality of contact electrodes made of the first material, and formed in regions corresponding with the lower storage electrodes.
16 . The array substrate of claim 15 , wherein the gate insulating sub-layers are formed by application of different deposition rates and flow of gases during a deposition process.
17 . The array substrate of claim 15 , wherein the lower storage electrode and the pixel electrode are each formed with at least one of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
18 . The array substrate of claim 15 , wherein the gate insulating layer is configured to function as a dielectric.
19 . The array substrate of claim 18 , wherein the pixel electrode is configured to function as an upper storage electrode in a storage capacitor formed by the pixel electrode, the lower storage electrode and the gate insulating layer formed therebetween.