IP Library Granted Patent US 8,704,450
Granted Patent B2
US 8,704,450 · App. 13/037,353 · Granted Apr 22, 2014

Flash LED controller

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,704,450
App. No.
13/037,353
Granted
Apr 22, 2014
Kind
B2
Abstract

The invention provides integrated power supplies, circuit drivers, and control methods for relatively high-current drivers, usable with common battery power sources. Preferred embodiments include one or more high series resistance super-capacitors electrically connected with a power. A low resistance driver circuit regulates power supplied from the super-capacitors to the load.

Claims (25)

1. A circuit comprising:

a first MOSFET transistor including a first drain, a first gate, and a first source;

a second MOSFET transistor including a second drain, a second gate, and a second source;

a third MOSFET transistor including a third drain, a third gate, and a third source;

a fourth MOSFET transistor including a fourth drain, a fourth gate, and a fourth source; and

a fifth MOSFET transistor including a fifth drain, a fifth gate, and a fifth source;

wherein the first source and the second source are each connected to a voltage supply,

the first gate and the second gate are each connected to the first drain and the fifth drain,

the fifth source is connected to the fourth drain,

the third source and the fourth source are each connected to ground, and

the third drain is connected to a load.

2. The circuit of claim 1 , wherein the first and second MOSFET transistors are p-channel type and the third, fourth, and fifth MOSFET transistors are n-channel type.

3. The circuit of claim 1 , further comprising:

a first resistor including a first terminal and a second terminal;

a second resistor including a third terminal and a fourth terminal;

a first opamp including a first positive input, a first negative input, and a first output; and

a second opamp including a second positive input, a second negative input, and a second output,

wherein the second positive input is connected to the third drain,

the second negative input is connected to the fifth source,

the second output is connected to the fifth gate,

the first positive input is connected to the third terminal and a current source,

the first negative input is connected to the second drain and the first terminal,

the first output is connected to the third gate and the fourth gate,

the second terminal is connected to ground, and

the fourth terminal is connected to ground.

Assignments (4)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (040646/0799) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0544 →
SECURITY INTEREST Recorded Nov 17, 2016
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 040646/0799 →
SECURITY INTEREST Recorded May 28, 2015
From: TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 035732/0326 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2011
From: CHEN, WAYNE; KNIGHT, JONATHAN; TEGGATZ, ROSS; SMITH, BRETT; NARASIMHAN, TRICHY
To: TRIUNE IP LLC
Reel/Frame 026283/0523 →