Flat panel display
View Patent ↗A flat panel display includes; a first substrate, a white reflective layer disposed on the first substrate, a pixel electrode disposed on the white reflective, a second substrate disposed facing the first substrate, a common electrode disposed on the second substrate, and an electrooptic layer disposed between the pixel electrode and the common electrode, wherein the white reflective layer includes at least one of TiO 2 and BaSO 4 .
1. A flat panel display, comprising:
a first substrate on which a plurality of pixel domains is defined, each of the plurality of pixel domains comprising a thin film transistor domain and a display domain;
a gate line and a gate electrode disposed on the first substrate;
at least one gate insulating layer disposed on the gate line and the gate electrode;
a semiconductor layer disposed on the gate insulating layer;
a data line which crosses the gate line;
a source electrode electrically connected to the data line
a drain electrode disposed substantially opposite to the source electrode with respect to the semiconductor layer;
a passivation layer disposed on the data line, the source electrode, and the drain electrode;
a pixel electrode disposed on the passivation layer and connected to the drain electrode;
a second substrate disposed substantially opposite to the first substrate;
a common electrode disposed on the second substrate; and
an electrooptic layer disposed between the pixel electrode and the common electrode,
wherein the drain electrode overlaps with the pixel electrode in the thin film transistor domain and the display domain and the drain electrode comprises an upper drain electrode and a lower drain electrode and
the upper drain electrode is reflective.
2. The flat panel display of claim 1 , wherein the electrooptic layer comprises:
a hydrophobic insulating layer disposed on the pixel electrode;
a barrier rib disposed on the hydrophobic insulating layer and having an opening formed therein; and
a black oil layer disposed in the opening.
3. The flat panel display of claim 1 , wherein the upper drain electrode is made of metal comprising aluminum.
4. The flat panel display of claim 3 , wherein the lower drain electrode is made of metal comprising at least one of molybdenum and titanium.
5. The flat panel display of claim 1 , further comprising contact holes formed in the passivation layer and the upper drain electrode which expose the lower drain electrode,
wherein the pixel electrode is connected to the lower drain electrode through the contact holes.
6. The flat panel display of claim 1 , wherein the passivation layer includes a lower passivation layer and an upper passivation layer,
the lower passivation layer comprises an inorganic insulating material, and
the upper passivation layer comprises an organic insulating material.
7. The flat panel display of claim 1 , further comprising a color filter disposed between the passivation layer and the pixel electrode.
8. The flat panel display of claim 1 , wherein the color filter comprises a quantum dot.
9. A flat panel display, comprising:
a first substrate on which a plurality of pixel domains is defined, each of the plurality of pixel domains including a thin film transistor domain and a display domain;
a gate line and a gate electrode disposed on the first substrate;
a gate insulating layer disposed on the gate line and the gate electrode;
a semiconductor layer disposed on the gate insulating layer;
a data line which crosses the gate line;
a source electrode electrically connected with the data line;
a drain electrode disposed substantially opposite to the source electrode with respect to the semiconductor layer;
a passivation layer disposed on the data line, the source electrode, and the drain electrode;
a white reflective layer disposed on the passivation layer;
a pixel electrode disposed on the white reflective layer and connected to the drain electrode;
a second substrate disposed substantially opposite to the first substrate;
a common electrode disposed on the second substrate; and
an electrooptic layer disposed between the pixel electrode and the common electrode,
wherein the drain electrode overlaps with the pixel electrode in the thin film transistor domain and the display domain and includes an upper drain electrode and a lower drain electrode and
the upper drain electrode is reflective.
10. The flat panel display of claim 9 , wherein the white reflective layer comprises at least one of titanium oxide and barium sulfate.
11. The flat panel display of claim 10 , wherein the white reflective layer is about 20 wt % to about 80 wt % titanium oxide.
12. The flat panel display of claim 10 , wherein the white reflective layer is about 20 wt % to about 80 wt % barium sulfate.
13. The flat panel display of claim 10 , wherein the electrooptic layer comprises:
a hydrophobic insulating layer disposed on the pixel electrode;
a barrier rib disposed on the hydrophobic insulating layer and having an opening formed therein; and
a black oil layer disposed in the opening.
14. The flat panel display of claim 9 , wherein the upper drain electrode is made of metal comprising aluminum.
15. The flat panel display of claim 14 , wherein the lower drain electrode is made of metal comprising at least one of molybdenum and titanium.
16. The flat panel display of claim 9 , further comprising contact holes formed in the passivation layer, the upper drain electrode and the white reflective layer which expose the lower drain electrode,
wherein the pixel electrode is connected to the lower drain electrode through the contact holes.
17. The flat panel display of claim 9 , wherein the passivation layer includes a lower passivation layer and an upper passivation layer,
the lower passivation layer comprises an inorganic insulating material, and
the upper passivation layer comprises an organic insulating material.
18. The flat panel display of claim 9 , further comprising a color filter disposed between the white reflective layer and the pixel electrode.
19. The flat panel display of claim 18 , wherein the color filter comprises a quantum dot.