Decoder and apparatuses including the same

1. A decoder comprising:

a first decoder configured to iteratively decode input data, accumulate iteratively decoded data in bit units, compare an accumulated value obtained for each bit of the iteratively decoded data with a plurality of reference values, and output decision data and indicator data according to a comparison result; and

a second decoder configured to perform error correction on a symbol comprising the decision data according to the indicator data.

2. The decoder of claim 1 , wherein the first decoder comprises:

an iterative decoder configured to iteratively decode the input data and output the iteratively decoded data; and

a decision circuit configured to accumulate the iteratively decoded data in bit units, output first data as the decision data when the accumulated value is less than a first reference value among the plurality of reference values, output second data as the decision data when the accumulated value is greater than a second reference value greater than the first reference value among the plurality of reference values, and output third data as the decision data together with the indicator data when the accumulated value is between the first reference value and the second reference value.

3. The decoder of claim 2 , wherein the first data has one of values of “1” and “0”, the second data has the other of the values of “1” and “0”, and the third data has either of the values of “1” and “0” by default.

4. The decoder of claim 2 , wherein the first decoder further comprises a switching circuit configured to alternatingly transmit the iteratively decoded data to one of the second decoder and the decision circuit in response to a control signal output from the second decoder.

5. The decoder of claim 1 , wherein the first decoder comprises:

an iterative decoder configured to output the iteratively decoded data;

a demultiplexer connected to an output terminal of the iterative decoder;

an accumulator configured to accumulate the iteratively decoded data output from a second output terminal of the demultiplexer in bit units and output the accumulated value;

a decision unit configured to output first data as the decision data when the accumulated value is less than a first reference value among the plurality of reference values, output second data as the decision data when the accumulated value is greater than a second reference value greater than the first reference value among the plurality of reference values, and output third data as the decision data when the accumulated value is between the first reference value and the second reference value; and

a multiplexer configured to transmit the iteratively decoded data output from a first output terminal of the demultiplexer or the decision data to the second decoder.

6. The decoder of claim 5 , wherein the decision unit transmits the indicator data to the second decoder when the accumulated value is between the first reference value and the second reference value.

7. The decoder of claim 5 , wherein the decision unit further outputs a flag when the accumulated value is between the first reference value and the second reference value; and

wherein the first decoder further comprises an error symbol detector configured to generate the indicator data including position information of the symbol in response to the flag.

8. The decoder of claim 5 , wherein the iterative decoder performs iterative decoding on the input data for a first number of iterations or performs iterative decoding on the input data for a second number more of iterations addition to the first number of iterations in response to a control signal output from the second decoder.

9. The decoder of claim 1 , wherein when an uncorrectable error exists in the iteratively decoded data output from the first decoder, the second decoder transmits a control signal to the first decoder to increase a number of iterations performed by the first decoder before the iteratively decoded data is accumulated in bit units; and

wherein the first decoder accumulates the iteratively decoded data in bit units for a number of iterations corresponding to an increment in response to the control signal.

10. A data processing system comprising:

a decoder comprising:

a first decoder configured to iteratively decode input data, accumulate iteratively decoded data in bit units, compare an accumulated value obtained for each bit of the iteratively decoded data with a plurality of reference values, and output decision data and indicator data according to a comparison result; and

a second decoder configured to perform error correction on a symbol comprising the decision data according to the indicator data; and

a processor configured to process data on which error correction has been performed by the decoder.

11. A controller to control an operation of a hard disk drive, the controller comprising:

a first decoder configured to iteratively decode input data, accumulate iteratively decoded data in bit units, compare an accumulated value obtained for each bit of the iteratively decoded data with a plurality of reference values, and output decision data and indicator data according to a comparison result; and

a second decoder configured to perform error correction on a symbol comprising the decision data according to the indicator data.

12. The controller of claim 11 , wherein the first decoder comprises:

an iterative decoder configured to iteratively decode the input data and output the iteratively decoded data; and

a decision circuit configured to accumulate the iteratively decoded data in bit units, output first data as the decision data when the accumulated value is less than a first reference value among the plurality of reference values, output second data as the decision data when the accumulated value is greater than a second reference value greater than the first reference value among the plurality of reference values, and output third data as the decision data together with the indicator data when the accumulated value is between the first reference value and the second reference value.

13. The controller of claim 12 , wherein the first decoder further comprises a switching circuit configured to transmit the iteratively decoded data to the second decoder or the decision circuit in response to a control signal output from the second decoder.

14. The controller of claim 11 , wherein the first decoder comprises:

an iterative decoder configured to output the iteratively decoded data;

a demultiplexer connected to an output terminal of the iterative decoder;

an accumulator configured to accumulate the iteratively decoded data output from a second output terminal of the demultiplexer in bit units and output the accumulated value;

a decision unit configured to output first data as the decision data when the accumulated value is less than a first reference value among the plurality of reference values, output second data as the decision data when the accumulated value is greater than a second reference value greater than the first reference value among the plurality of reference values, and output third data as the decision data when the accumulated value is between the first reference value and the second reference value; and

a multiplexer configured to transmit the iteratively decoded data output from a first output terminal of the demultiplexer or the decision data to the second decoder.

15. The controller of claim 14 , wherein the decision unit transmits the indicator data to the second decoder when the accumulated value is between the first reference value and the second reference value.

16. The controller of claim 11 , wherein when an uncorrectable error exists in the iteratively decoded data output from the first decoder, the second decoder transmits a control signal to the first decoder to increase a number of iterations performed by the first decoder before the iteratively decoded data is accumulated in bit units; and

wherein the first decoder accumulates the iteratively decoded data in bit units for a number of iterations corresponding to an increment in response to the control signal.

17. A hard disk drive comprising:

a disk;

a head configured to read an analog signal from the disk;

a pre-amplifier configured to amplify the analog signal read by the head; and

a controller comprising a first decoder configured to iteratively decode input data corresponding to an analog signal output from the pre-amplifier, accumulate iteratively decoded data in bit units, compare an accumulated value obtained for each bit of the iteratively decoded data with a plurality of reference values, and output decision data and indicator data according to a comparison result; and a second decoder configured to perform error correction on a symbol comprising the decision data according to the indicator data.

18. The hard disk drive of claim 17 , wherein the first decoder comprises:

an iterative decoder configured to iteratively decode the input data and output the iteratively decoded data; and

a decision circuit configured to accumulate the iteratively decoded data in bit units, output first data as the decision data when the accumulated value is less than a first reference value among the plurality of reference values, output second data as the decision data when the accumulated value is greater than a second reference value greater than the first reference value among the plurality of reference values, and output third data as the decision data together with the indicator data when the accumulated value is between the first reference value and the second reference value.