IP Library Patent Application 13038781
Patent Application
App. No. 13/038,781

METHOD OF FORMING LDD OF TFT, METHOD OF FABRICATING TFT AND ORGANIC LIGHT EMITTING DEVICE USING THE METHOD

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Patent No.
US None
App. No.
13/038,781
Abstract

A method of forming a lightly doped drain (LDD) of a thin film transistor (TFT) is disclosed. The method includes the following steps. A gate electrode is formed on a front side of a substrate. A gate insulating layer is formed on the gate electrode and the front side of the substrate. An activation layer is formed on the gate insulating layer. Low-concentration ion implantation is performed on the activation layer via a back side of the substrate. High-concentration ion implantation is performed on the activation layer that has been subjected to the low-concentration ion implantation, via the front side of the substrate, thereby forming a low-concentration impurity region and a high-concentration impurity region in the activation layer. The method may further include forming a high-concentration ion implantation mask on the activation layer.

Claims (46)

1 . A method of forming a lightly doped drain (LDD) of a thin film transistor (TFT), the method comprising:

forming a gate electrode on a front side of a substrate;

forming a gate insulating layer on the gate electrode and the front side of the substrate;

forming an activation layer on the gate insulating layer;

performing low-concentration ion implantation on the activation layer via a back side of the substrate; and

performing high-concentration ion implantation on the activation layer that has been subjected to the low-concentration ion implantation, via the front side of the substrate, thereby forming a low-concentration impurity region and a high-concentration impurity region in the activation layer.

2 . The method of claim 1 , wherein the low-concentration ion implantation is performed using the gate electrode as a mask.

3 . The method of claim 1 , wherein the low-concentration ion implantation is performed at inclination angles with respect to the substrate.

4 . The method of claim 3 , wherein the gate electrode comprises side surfaces inclined at inclination angles smaller than 90 degrees with respect to the substrate.

5 . The method of claim 3 , wherein the inclination angles are controlled to be such that the low-concentration ion implantation is performed on a portion of the activation layer overlapping the gate electrode.

6 . The method of claim 1 , wherein the high-concentration ion implantation is performed in a direction perpendicular to the substrate.

7 . The method of claim 1 , further comprising forming a high-concentration ion implantation mask after the low-concentration ion implantation but before the high-concentration ion implantation.

8 . The method of claim 1 , further comprising forming a high-concentration ion implantation mask after forming the activation layer but before the low-concentration ion implantation.

9 . The method of claim 1 , further comprising forming a high-concentration ion implantation mask after forming the activation layer, wherein a width of the high-concentration ion implantation mask is greater than a width of the gate electrode.

10 . The method of claim 1 , wherein the low-concentration ion implantation and the high-concentration ion implantation are performed using an n-type semiconducting material.

11 . The method of claim 10 , wherein the low-concentration ion implantation and the high-concentration ion implantation are performed using phosphorous (P) or arsenic (As).

12 . The method of claim 1 , wherein low-concentration ion implantation and the high-concentration ion implantation are performed using a p-type semiconducting material.

13 . The method of claim 12 , wherein the low-concentration ion implantation and the high-concentration ion implantation are performed using boron (B).

14 . The method of claim 1 , wherein the activation layer comprises polycrystalline silicon.

15 . The method of claim 14 , wherein the forming of the activation layer comprises:

forming an amorphous silicon layer on the gate insulating layer; and

crystallizing the amorphous silicon layer.

16 . The method of claim 15 , wherein the crystallizing of the amorphous silicon layer is performed by excimer laser annealing (ELA).

17 . The method of claim 15 , wherein the crystallizing of the amorphous silicon layer is performed by heat treatment using a metallic catalyst.

18 . The method of claim 1 , further comprising forming a buffer layer on the substrate before the forming of the gate electrode.

19 . A method of forming a thin film transistor (TFT), the method comprising:

forming a gate electrode on a front side of a substrate;

forming a gate insulating layer on the gate electrode and the front side of the substrate;

forming an activation layer on the gate insulating layer;

performing low-concentration ion implantation on the activation layer via a back side of the substrate;

performing high-concentration ion implantation on the activation layer that has been subjected to the low-concentration ion implantation, via the front side of the substrate, thereby forming a low-concentration impurity region and a high-concentration impurity region in the activation layer;

forming a first interlayer insulating layer on the activation layer that has been subjected to the high-concentration ion implantation and the gate insulating layer; and

forming a source/drain electrode that passes through the first interlayer insulating layer and contacts the high-concentration impurity region.

20 . A method of forming an organic electroluminescent device, the method comprising:

forming a gate electrode on a front side of a substrate;

forming a gate insulating layer on the gate electrode and the front side of the substrate;

forming an activation layer on the gate insulating layer;

performing low-concentration ion implantation on the activation layer via a back side of the substrate;

performing high-concentration ion implantation on the activation layer that has been subjected to the low-concentration ion implantation, via the front side of the substrate, thereby forming a low-concentration impurity region and a high-concentration impurity region in the activation layer;

forming a first interlayer insulating layer on the activation layer that has been subjected to the high-concentration ion implantation and the gate insulating layer;

forming a source/drain electrode that passes through the first interlayer insulating layer and contacts the high-concentration impurity region;

forming a second interlayer insulating layer on the first interlayer insulating layer and the source/drain electrode;

forming a first pixel electrode that passes through the second interlayer insulating layer and contacts the source/drain electrode, and extends onto the second interlayer insulating layer;

forming a pixel defining layer on the second interlayer insulating layer and the first pixel electrode;

forming an organic layer comprising an emission layer on a portion of the first pixel electrode defined by the pixel defining layer; and

forming a second pixel electrode on the organic layer.

Assignments (2)
MERGER Recorded Aug 20, 2012
From: SAMSUNG MOBILE DISPLAY CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 028816/0306 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2011
From: KIM, YOUNG-IL
To: SAMSUNG MOBILE DISPLAY CO., LTD.
Reel/Frame 025925/0368 →