Method of manufacturing semiconductor device
View Patent ↗A method for manufacturing a semiconductor device includes the step of polishing a conductive film formed over a semiconductor substrate. The conductive film is formed by a barrier film that is in contact with second and third interlayer insulating films, and a copper film that is in contact with the barrier film. A polishing surface of a second polishing pad for polishing and removing the barrier film and the third interlayer insulating film has a lower pore area ratio than a polishing surface of a first polishing pad for polishing and removing the copper film.
1. A method for manufacturing a semiconductor device, comprising step of:
forming a groove in an insulating film, the insulating film being formed over a semiconductor substrate;
forming a barrier film and a metal film sequentially over the insulating film after forming the groove;
performing a first chemical mechanical polishing (CMP), with a first polishing pad, on the metal film to remove a portion of the metal film in a region other than the groove; and
performing a second CMP, with a second polishing pad, on the barrier film and the insulating film to remove a portion of the barrier film in the region other than the groove and an upper portion of the insulating film, wherein:
a pore area ratio of a polishing pad is defined as a proportion, represented in percent, of an area of a wafer that does not contact the polishing pad to a total area of the wafer,
a polishing surface of the first polishing pad has a first pore area ratio and a polishing surface of the second polishing pad has a second pore area ratio, and
the first pore area ratio is larger than the second pore area ratio.
2. The method of claim 1 , wherein
the second pore area ratio is equal to or more than 10 percent and equal to or less than 23X 1.2 percent, where X is hardness of the insulating film in a GPa unit.
3. The method of claim 1 , wherein
the first pore area ratio is equal to or more than 23X 1.2 percent and equal to or less than 90 percent, where X is hardness of the insulating film in a GPa unit.
4. The method of claim 1 , wherein
the insulating film has a relative dielectric constant of 3.0 or less.
5. The method of claim 1 , wherein
the insulating film is formed by a first insulating film having a relative dielectric constant of more than 3.0 as an upper layer, and a second insulating film having a relative dielectric constant of 3.0 or less as a lower layer.
6. The method of claim 5 , wherein
the entire first insulating film is polished and removed in the step of performing the second CMP.
7. A method for manufacturing a semiconductor device, comprising step of:
forming an insulating film over a semiconductor substrate;
performing a first chemical mechanical polishing (CMP), with a first polishing pad, on the insulating film to remove an upper portion of the insulating film;
performing a second CMP, with a second polishing pad which is different from the first polishing pad, on the insulating film, after the step of performing the first CMP, wherein:
a pore area ratio of a polishing pad is defined as a proportion, represented in percent, of an area of a wafer that does not contact the polishing pad to a total area of the wafer,
a polishing surface of the first polishing pad has a first pore area ratio and a polishing surface of the second polishing pad has a second pore area ratio, and
the first pore area ratio is larger than the second pore area ratio.
8. The method of claim 7 , wherein
the second pore area ratio is equal to or more than 10 percent and equal to or less than 23X 1.2 percent, where X is hardness of the insulating film in a GPa unit.
9. The method of claim 7 , wherein
the first pore area ratio is equal to or more than 23X 1.2 percent and equal to or less than 90 percent, where X is hardness of the insulating film in a GPa unit.
10. The method of claim 7 , wherein
the insulating film has a relative dielectric constant of 3.0 or less.