Electronic device for controlling a current
View Patent ↗An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground.
1. An apparatus comprising:
a squib pin;
a ground pin;
a squib coupled to the squib pin;
a control loop;
a first MOS transistor that is coupled between the squib pin and the ground pin, wherein the first transistor is controlled by the control loop;
a resistor that is coupled to the control loop;
a second MOS transistor that is coupled to the resistor;
a third MOS transistor that is coupled between the second transistor and the ground pin, wherein the third MOS transistor is controlled by the control loop; and
an amplifier that is coupled to the squib pin and a node between the second transistor and the third transistor and that is coupled to the gate of the second transistor, wherein the amplifier equalizes the drain-source voltages of first and third MOS transistors.
2. The apparatus of claim 1 , wherein the control loop further comprises:
a current source;
a current mirroring circuit that is coupled to the current source and the resistor;
a voltage divider that is coupled to the current mirroring circuit; and
a control circuit that is coupled to the current mirroring circuit and the gates of the first and third MOS transistors.
3. The apparatus of claim 2 , wherein the resistor further comprises a first resistor, and wherein the current mirroring circuit further comprises:
a first current mirror that is coupled to the current source;
a plurality of bias transistors that are coupled to the first current mirror and the voltage divider;
a second current mirror that is coupled to the plurality of bias transistors and the first resistor; and
a second resistor that is coupled to the second current mirror.
4. The apparatus of claim 3 , wherein the first and second MOS transistors are substantially matched.
5. The apparatus of claim 4 , wherein ratio of the size of the third MOS transistor to the first transistor is M:1.
6. The apparatus of claim 5 , wherein the current source further comprises a first current source, and wherein the control circuit further comprises:
a second current source; and
a source-follower that is coupled to the second current source, the first current mirror, and the gates of the first and third MOS transistors.
7. The apparatus of claim 5 , wherein the control circuit further comprises a diode that is coupled to the voltage divider, the first current mirror and the gates of the first and third MOS transistors.
8. An apparatus comprising:
a squib pin;
a ground pin;
a squib that is coupled to the squib pin;
a capacitor coupled to the squib pin;
a control loop;
a first MOS transistor that is coupled between the squib pin and the ground pin, wherein the first transistor is controlled by the control loop;
a resistor that is coupled to the control loop;
a second MOS transistor that is coupled to the resistor;
a third MOS transistor that is coupled between the second transistor and the ground pin, wherein the third MOS transistor is controlled by the control loop; and
an amplifier that is coupled to the squib pin and a node between the second transistor and the third transistor and that is coupled to the gate of the second transistor, wherein the amplifier equalizes the drain-source voltages of first and third MOS transistors.
9. The apparatus of claim 8 , wherein the control loop further comprises:
a current source;
a current mirroring circuit that is coupled to the current source and the resistor;
a voltage divider that is coupled to the current mirroring circuit; and
a control circuit that is coupled to the current mirroring circuit and the gates of the first and third MOS transistors.
10. The apparatus of claim 9 , wherein the resistor further comprises a first resistor, and wherein the current mirroring circuit further comprises:
a first current mirror that is coupled to the current source;
a plurality of bias transistors that are coupled to the first current mirror and the voltage divider;
a second current mirror that is coupled to the plurality of bias transistors and the first resistor; and
a second resistor that is coupled to the second current mirror.
11. The apparatus of claim 10 , wherein the first and second MOS transistors are substantially matched.
12. The apparatus of claim 11 , wherein ratio of the size of the third MOS transistor to the first transistor is M:1.
13. The apparatus of claim 12 , wherein the current source further comprises a first current source, and wherein the control circuit further comprises:
a second current source; and
a source-follower that is coupled to the second current source, the first current mirror, and the gates of the first and third MOS transistors.
14. The apparatus of claim 12 , wherein the control circuit further comprises a diode that is coupled to the voltage divider, the first current mirror and the gates of the first and third MOS transistors.