DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

1 . A display device comprising:

a substrate having a pixel region, a transistor region, and a capacitor region;

a transistor formed in the transistor region, wherein the transistor comprises i) an active layer formed over the substrate, ii) a gate insulating layer formed on the active layer, iii) a gate electrode formed on the gate insulating layer, and iv) a first interlayer insulating layer covering the gate electrode and formed on the gate insulating layer, v) a second interlayer insulating layer formed on the first interlayer insulating layer and vi) a source electrode and a drain electrode electrically connected to the active layer; and

a capacitor formed in the capacitor region, wherein the capacitor comprises i) a lower electrode formed on the gate insulating layer and ii) an upper electrode formed on the first interlayer insulating layer, and wherein the upper electrode is formed substantially directly above the lower electrode,

wherein the surface area of the lower electrode is less than the surface area of the upper electrode.

2 . The display device as claimed in claim 1 , wherein the first interlayer insulating layer is formed at least partially of an inorganic insulating material and wherein the second interlayer insulating layer is formed at least partially of an organic insulating material.

3 . The display device as claimed in claim 1 , wherein the lower electrode is formed of the same material as that of the gate electrode and is covered by the first interlayer insulating layer, and wherein the upper electrode is made of the same material as those of the source electrode and the drain electrode.

4 . The display device as claimed in claim 1 , wherein the upper electrode penetrates the second interlayer insulating layer so as to contact the first interlayer insulating layer.

5 . The display device as claimed in claim 1 , wherein the source electrode and the drain electrode penetrate i) the gate insulating layer and ii) the first and second interlayer insulating layers to be electrically connected to the active layer.

6 . The display device as claimed in claim 1 , further comprising a passivation layer formed on the second interlayer insulating layer and covering the source electrode, the drain electrode, and the upper electrode.

7 . The display device as claimed in claim 6 , wherein the passivation layer is formed of the same material as that of the second interlayer insulating layer.

8 . The display device as claimed in claim 1 , further comprising a semiconductor layer formed substantially directly below the lower electrode, wherein the semiconductor layer is covered by the gate insulating layer.

9 . The display device as claimed in claim 1 , wherein the second interlayer insulating layer is thicker than the first interlayer insulating layer.

10 . A method of manufacturing a display device, the method comprising:

forming an active layer in a transistor region of a substrate having a pixel region, the transistor region and a capacitor region;

forming a gate insulating layer over the substrate so as to cover the active layer;

forming i) a gate electrode on the gate insulating layer in the transistor region and ii) a lower electrode in the capacitor region;

forming a first interlayer insulating layer on the gate insulating layer so as to cover the gate electrode and the lower electrode;

forming a second interlayer insulating layer on the first interlayer insulating layer;

removing first, second and third portions of the second interlayer insulating layer, wherein the first and second portions are formed substantially directly above the active layer, wherein the third portion is partially removed and formed substantially directly above the lower electrode;

removing part of the first interlayer insulating layer and part of the gate insulating layer so as to expose the active layer;

removing the remaining third portion of the second interlayer insulating layer to expose the first interlayer insulating layer in the capacitor region; and

forming i) an upper electrode on the exposed portion of the first interlayer insulating layer in the capacitor region and ii) a source electrode and a drain electrode on the exposed portion of the active layer in the transistor region,

wherein the surface area of the lower electrode is less than the surface area of the upper electrode.

11 . The method as claimed in claim 10 , wherein the first interlayer insulating layer has a raised portion formed substantially directly above the lower electrode so as to protrude toward the second interlayer insulating layer, wherein the second interlayer insulating layer has a fourth portion formed on the raised portion to be adjacent to the removed third portion of the second interlayer insulating layer in the capacitor region, and wherein the thickness of the fourth portion is in the range of about 500 Å to about 1000 Å.

12 . The method as claimed in claim 10 , wherein the second interlayer insulating layer is thicker than the first interlayer insulating layer.

13 . The method as claimed in claim 10 , wherein the lower electrode is formed substantially simultaneously with the gate electrode and wherein the upper electrode is formed substantially simultaneously with the source electrode and the drain electrode.

14 . A method of manufacturing a display device comprising:

forming a transistor in a transistor region of a substrate having a pixel region, the transistor region, and a capacitor region;

forming a capacitor including a lower electrode and an upper electrode in the capacitor region, wherein an interlayer insulating layer is interposed between the lower electrode and the upper electrode;

forming a passivation layer on the transistor and the capacitor; and

forming an electrode to be electrically connected to the transistor on the passivation layer,

wherein the surface area of the lower electrode is less than the surface area of the upper electrode.

15 . The method as claimed in claim 14 , wherein the lower electrode is formed substantially directly below the upper electrode, and wherein the width of the lower electrode is less than or substantially equal to that of the upper electrode.

16 . The method as claimed in claim 14 , wherein the upper electrode is substantially thicker than the lower electrode.

17 . The method as claimed in claim 14 , wherein the forming of the transistor comprises:

forming an active layer in the transistor region;

forming a gate insulating layer on the active layer;

forming a gate electrode on the gate insulating layer to be substantially directly above the active layer;

forming an inorganic insulating layer on the gate electrode;

forming an organic insulating layer on the inorganic insulating layer; and

forming a source electrode and a drain electrode that penetrate the inorganic insulating layer and the organic insulating layer, where the source and drain electrodes are electrically connected to the active layer.

18 . The method as claimed in claim 14 , wherein the forming of the capacitor comprises:

forming a gate insulating layer in the capacitor region;

forming the lower electrode on the gate insulating layer;

forming an inorganic insulating layer on the lower electrode;

forming an organic insulating layer, having a step, on the inorganic insulating layer;

removing a first portion of the organic insulating layer, wherein the first portion of the organic insulating layer is formed substantially directly above the lower electrode; and

forming the upper electrode in the removed first portion of the organic insulating layer so as to contact the inorganic insulating layer.

19 . The method as claimed in claim 18 , wherein the inorganic insulating layer has a raised portion formed substantially directly above the lower electrode so as to protrude toward the organic insulating layer, wherein the organic insulating layer has a second portion formed on the raised portion to be adjacent to the removed first portion of the organic insulating layer in the capacitor region, and wherein the thickness of the second portion is in the range of about 500 Å to about 1000 Å.

20 . The method as claimed in claim 18 , further comprising forming a semiconductor layer in the capacitor region, before forming the gate insulating layer, wherein the semiconductor layer is covered by the gate insulating layer.