System and method for multiple PoE power supply management
A system and method for multiple power over Ethernet (PoE) power supply management. Power supply status signals indicative of an operating condition of a plurality of PoE power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of PoE power supplies into a powering decision for each of the Ethernet ports served by the PSE controller chip within one microsecond.
1. A system, comprising
a first plurality of power supplies;
a logic block that is configured to receive a power supply status signal from each of the first plurality of power supplies, the logic block being configured to generate a second plurality of status signals based on the first plurality of power supply status signals, wherein the first plurality of power supply status signals is greater in number than the second plurality of status signals, wherein the second plurality of status signals indicate an operational status of more than one of the first plurality of power supplies; and
a controller chip that is configured to receive the second plurality of status signals from the logic block, the controller chip being further configured to control an application of power to a plurality of ports based on an application of pre-defined rules that map the operational status of more than one of the first plurality of power supplies as indicated by the values of the second plurality of status signals to a powering state for the plurality of ports.
2. The system of claim 1 , wherein each of the first plurality of power supply status signals indicate an operating condition for a respective one of the first plurality of power supplies.
3. The system of claim 1 , wherein the control of the controller chip is based on pre-configured combination logic.
4. The system of claim 1 , wherein the control of the controller chip is based on a software module.
5. The system of claim 1 , wherein the control of the controller chip is based on a relative power priority levels for the plurality of ports.
6. The system of claim 1 , wherein the logic block is a complex programmable logic device.
7. The system of claim 1 , wherein the logic block is a field programmable gate array.
8. A power over Ethernet controller chip, comprising:
a first plurality of inputs that are configured to receive a corresponding first plurality of status signals from a logic block, the logic block producing the first plurality of status signals based on a second plurality of power supply status signals, each of the second plurality of power supply status signals being indicative of an operating condition of a respective plurality of power supplies, wherein the first plurality of status signals is less in number than the second plurality of power supply status signals, and indicate an operational status of more than one of the plurality of power supplies; and
a controller that controls an application of power on a plurality of ports based on the first plurality of status signals, wherein the control by the controller is based on an application of pre-defined rules that map the operational status of more than one of the plurality of power supplies as indicated by the values of the first plurality of status signals to a powering state for a plurality of ports.
9. The power over Ethernet controller chip of claim 8 , wherein the control is based on pre-configured combination logic.
10. The power over Ethernet controller chip of claim 8 , wherein the control is based on a software module.
11. The power over Ethernet controller chip of claim 8 , wherein the control is based on a relative power priority levels for the plurality of ports.
12. The power over Ethernet controller chip of claim 8 , wherein the logic block is a complex programmable logic device.
13. The power over Ethernet controller chip of claim 8 , wherein the logic block is a field programmable gate array.
14. A method, comprising:
receiving, in a logic block, a power supply status signal from each of a corresponding first plurality of power supplies;
generating, by the logic block, a second plurality of status signals based on the first plurality of power supply status signals, wherein the first plurality of power supply status signals is greater in number than the second plurality of status signals and indicate an operational status of more than one of the first plurality of power supplies;
determining, by a controller, a first powering state of a plurality of ports based on the second plurality of status signals, the determination being based on an application of pre-defined rules that map the operational status of more than one of the first plurality of power supplies as indicated by the values of the second plurality of status signals to a powering state for the plurality of ports; and
determining, by the controller, using the pre-defined rules, a second powering state of the plurality of ports upon a change in the second plurality of status signals.
15. The method of claim 14 , wherein the change in operating condition of the second plurality of status signals corresponds to a power supply going down.
16. The method of claim 14 , wherein the change in operating condition of the second plurality of status signals corresponds to a power supply coming up.
17. The method of claim 14 , wherein the pre-defined rules are based on pre-configured combination logic.
18. The method of claim 14 , wherein the pre-defined rules are based on a software module.
19. The method of claim 14 , wherein the receiving comprises receiving in a complex programmable logic device.
20. The method of claim 14 , wherein the receiving comprises receiving in field programmable gate array.