Transistor substrate and manufacturing method of the same

1. A transistor substrate, comprising:

a semiconductor layer arranged on a base layer;

a first layer arranged on the semiconductor layer and having a first light transmissivity;

source and drain electrodes, the source electrode arranged on a first side of the semiconductor layer and extending onto a first portion of the first layer, the drain electrode arranged on a second and opposite side of the semiconductor layer and extending onto a second portion of the first layer and separated from the source electrode by a distance;

a second layer arranged between the first layer and the source and drain electrodes and having a second light transmissivity that is lower than the first light transmissivity;

a gate insulating layer arranged on the first layer; and

a gate electrode arranged on the gate insulating layer.

2. The transistor substrate of claim 1 , wherein the first layer comprises a material that has etch selectivity with respect to the source and drain electrodes and the second layer.

3. The transistor substrate of claim 1 , wherein inner sides of the source and drain electrodes and an inner side of the second layer are arranged on a same plane.

4. The transistor substrate of claim 1 , wherein outer sides of the source and drain electrodes and an outer side of the semiconductor layer are arranged on a same plane.

5. The transistor substrate of claim 1 , wherein an outer side of the first layer and an outer side of the second layer are arranged on a same plane.

6. The transistor substrate of claim 1 , wherein the source and drain electrodes directly contact the semiconductor layer.

7. The transistor substrate of claim 1 , wherein the first light transmissivity is greater than 50% and less than 100%, and the second light transmissivity is greater than 0% and less than 50%.

8. The transistor substrate of claim 1 , wherein the first layer comprises silicon oxide, and the second layer comprises a material selected from a group consisting of amorphous silicon and doped amorphous silicon.

9. The transistor substrate of claim 1 , wherein the source and drain electrodes comprise:

a plurality of ohmic contact layers; and

a metal layer arranged on the ohmic contact layers.

10. The transistor substrate of claim 1 , wherein a portion of the semiconductor layer on which the first layer is not arranged comprises impurities.

11. The transistor substrate of claim 1 , further comprising an alignment key spaced apart from the semiconductor layer by a distance and comprising a third layer comprised of a same material as that of the second layer.

12. The transistor substrate of claim 11 , wherein the alignment key further comprises a fourth layer arranged underneath the third layer and comprising a same material as that of the first layer.

13. A method of manufacturing a transistor substrate, comprising:

sequentially forming a semiconductor layer, a first layer and a second layer on a base layer by patterning the first and second layers using a first photomask process so that outer sides of the first and second layers are arranged on a same plane, wherein the first layer has a first light transmissivity and the second layer has a second and lower light transmissivity;

forming source and drain electrodes by depositing a material for the source and drain electrodes on the resultant structure of the first photomask process and patterning the deposited material via a second photomask process, wherein the source electrode is connected to a first side of the semiconductor layer and extends onto a first portion of the second layer, and the drain electrode is connected to a second and opposite side of the semiconductor layer and extends onto a second portion of the second layer and is spaced-apart from the source electrode by a distance, wherein inner sides of the source and drain electrodes and an inner side of the second layer are arranged on a same plane; and

forming a gate electrode at a location that corresponds to the semiconductor layer by depositing an insulating layer and then a material for a gate electrode on the resultant structure of the second photomask process and then patterning the material for the gate electrode via a third photomask.

14. The method of claim 13 , further comprising forming alignment keys spaced apart from the semiconductor layer by a distance and at corners of the base layer, the alignment keys comprising a third layer comprised of a same material as that of the second layer.

15. The method of claim 14 , wherein the alignment keys further comprise a fourth layer arranged underneath the third layer and comprising a same material as that of the first layer.

16. The method of claim 13 , wherein the source and drain electrodes are patterned so that outer sides of the source and drain electrodes and an outer side of the semiconductor layer are arranged on a same plane.

17. The method of claim 13 , wherein the first layer comprises a material that has an etch selectivity with respect to the source and drain electrodes and the second layer.

18. The method of claim 13 , further comprising forming ohmic contact layers by depositing a material for the ohmic contact layers and then patterning the material for the ohmic contact layers during the second photomask process.

19. The method of claim 18 , wherein the second photomask process further comprises etching the second layer in a same process as the patterning of the material for the ohmic contact layers.

20. The transistor substrate manufactured by the method of claim 13 , further comprised of:

alignment keys formed at corners of the base layer and spaced apart from the semiconductor layer by a distance, the alignment keys comprising a third layer comprised of a same material as that of the second layer; and

the first layer comprising a material that has etch selectivity with respect to the source and drain electrodes and the second layer.