IP Library Granted Patent US 8,605,847
Granted Patent B2
US 8,605,847 · App. 13/043,908 · Granted Dec 10, 2013

Receiver training with cycle slip detection and correction

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Quick Facts
Patent No.
US 8,605,847
App. No.
13/043,908
Granted
Dec 10, 2013
Kind
B2
Abstract

In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Claims (47)

1. An apparatus for a receiver comprising:

a clock and data recovery (CDR) module adapted to generate a local clock, the CDR module comprising:

an eye monitor configured to generate a data eye from a data stream subject to equalization, the eye monitor including a transition sampler, an intermediate sampler and a data sampler, each sampler having timing derived from the local clock; and

a cycle slip detector configured to detect a CDR out-of-lock condition based on outputs of the transition, intermediate, and data samplers with respect to signal transitions between quadrants, and

an adaptation module configured to adaptively set parameters of one or more corresponding devices to the data stream based upon the local clock of the CDR module,

wherein the apparatus suspends adaptation of the parameters of at least one of the devices based on detection of the CDR out-of-lock condition.

2. The apparatus of claim 1 , wherein the one or more devices include at least one of an analog front end equalizer (AFE), a decision feedback equalizer (DFE), and a gain circuit.

3. The apparatus of claim 1 , wherein the apparatus suspends adaptation during an acquisition period, and the adaptation module is further configured to obtain an adaptation convergence over a number, N, of iterations, where N, is a positive integer.

4. The apparatus of claim 3 , wherein the adaptation module checks for the CDR out-of-lock condition after adaptation of the parameters for a current device and,

if the CDR out-of-lock condition is detected, declares the parameters for the current device and the iteration invalid, restarts the CDR module, and moves to the next iteration,

otherwise, if a CDR lock condition is detected, the adaptation module declares the parameters for the current device of the iteration valid, and continues to adaptively set parameters for a next device.

5. The apparatus of claim 4 , wherein, during an iteration, the adaptation module adaptively sets the parameters of at least two of the devices in parallel before the adaptation module checks for the CDR out-of-lock condition.

6. The apparatus of claim 1 , further comprising an accumulator, wherein the cycle slip detector increments and decrements contents of the accumulator based on the signal transitions between quadrants.

7. The apparatus of claim 6 , wherein the cycle slip detector declares the CDR out-of-lock condition when the contents of the accumulator reaches a threshold value.

8. The apparatus of claim 1 , wherein the adaptation module is coupled to a transmitter configured to provide the data stream,

wherein the transmitter, based on an indication of the adaptation module, adaptively sets parameters of each device of the transmitter in a signal path of the data stream, each device comprising at least one of a gain, a filter, and an equalizer, and

wherein the transmitter suspends adaptively setting the parameters when the CDR out-of-lock condition is detected by notification by the receiver to the transmitter with a predefined protocol layer.

9. The apparatus of claim 1 , wherein the apparatus is embodied in a Serial DeSerializer (SerDes) device.

10. A method of operating a receiver comprising:

generating, with a clock and data recovery (CDR) module, a local clock, the CDR module comprising:

generating, with an eye monitor, a data eye from a data stream subject to equalization, the eye monitor including a transition sampler, an intermediate sampler and a data sampler, each sampler having timing derived from the local clock; and

detecting, with a cycle slip detector, a CDR out-of-lock condition based on outputs of the transition, intermediate, and data samplers with respect to signal transitions between quadrants, and

adaptively setting parameters of one or more corresponding devices to the data stream based upon the local clock of the CDR module, and

suspending adaptation of the parameters of at least one of the devices based on detection of the CDR out-of-lock condition.

11. The method of claim 10 , wherein, for the step of adaptively setting parameters, the one or more devices include at least one of an analog front end equalizer (AFE), a decision feedback equalizer (DFE), and a gain circuit.

12. The method of claim 10 , wherein suspending adaptation occurs during an acquisition period, and the method comprises obtaining an adaptation convergence over a number, N, of iterations, where N, is a positive integer.

13. The method of claim 12 , comprising checking for the CDR out-of-lock condition after adaptation of the parameters for a current device and,

if the CDR out-of-lock condition is detected, declaring the parameters for the current device and the iteration invalid, restarting the CDR module, and moving to the next iteration,

otherwise, if a CDR lock condition is detected, declaring the parameters for the current device of the iteration valid, and continuing to adaptively set parameters for a next device.

14. The method of claim 12 , wherein, during an iteration, the method comprises adaptively setting the parameters of at least two of the devices in parallel before checking for the CDR out-of-lock condition.

15. The method of claim 10 , further comprising incrementing and decrementing contents of an accumulator based on the signal transitions between quadrants.

16. The method of claim 15 , comprising:

comparing the contents of the accumulator to a threshold value; and

declaring the CDR out-of-lock condition when the contents of the accumulator reaches a threshold value.

17. The method of claim 10 , comprising:

providing the data stream by a transmitter;

generating, by the receiver, an indication of the presence or absence of the CDR out-of-lock condition;

adaptively setting parameters of one or more devices of the transmitter in a signal path of the data stream, each device at least one of a gain, a filter, and an equalizer, and

suspending, based on the indication, the adaptively setting the parameters in the presence of the CDR out-of-lock condition.

18. The method of claim 10 , wherein the method is embodied as steps executed by at least one processor of a Serial DeSerializer (SerDes) device.

19. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for adaptively setting parameters in a receiver, comprising the steps of:

generating, with a clock and data recovery (CDR) module, a local clock, the CDR module comprising:

generating, with an eye monitor, a data eye from a data stream subject to equalization, the eye monitor including a transition sampler, an intermediate sampler and a data sampler, each sampler having timing derived from the local clock; and

detecting, with a cycle slip detector, a CDR out-of-lock condition based on outputs of the transition, intermediate, and data samplers with respect to signal transitions between quadrants, and

adaptively setting parameters of one or more corresponding devices to the data stream based upon the local clock of the CDR module, and

suspending adaptation of the parameters of at least one of the devices based on detection of the CDR out-of-lock condition.

20. The non-transitory machine-readable storage medium of claim 19 , wherein, for the step of adaptively setting parameters, the one or more devices include at least one of an analog front end equalizer (AFE), a decision feedback equalizer (DFE), and a gain circuit.

Assignments (12)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
SECURITY INTEREST Recorded Nov 10, 2016
From: SKYLINE DISPLAYS, LLC
To: MB FINANCIAL BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 040583/0542 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2011
From: MOBIN, MOHAMMAD; TRAFFORD, MARK; LIU, YE; SINDALOVSKY, VLADIMIR; MALIPATIL, AMARESH
To: LSI CORPORATION
Reel/Frame 025926/0675 →