Method and System for High Speed, Low Power and Small Flip-Flops
A master-slave flip-flop may be operable to sense a signal, received by a slave circuit from a master circuit, at a pair of serially coupled NMOS transistors and/or at a pair of serially coupled PMOS transistors in the slave circuit. The flip-flop may generate a corresponding output signal at an output terminal based on the sensing of the signal received by the slave circuit. The flip-flop may receive, in a feedback path of the slave circuit, a SET signal. An inverted version of the SET signal may be received via a gate terminal of a PMOS transistor in the master circuit. The flip-flop may receive, in a feedback path of the master circuit, a RESET signal. The RESET signal may also be received via a gate of a NMOS transistor in the master circuit. The flip-flop may disable an input terminal utilizing the SET signal and/or the RESET signal.
1 . A method for flip-flop circuitry, the method comprising:
in a master-slave flip-flop comprising a master circuit, a slave circuit and an input control circuit:
sensing a signal received by said slave circuit from said master circuit at a pair of serially coupled NMOS transistors and/or at a pair of serially coupled PMOS transistors in said slave circuit, wherein:
a gate terminal of a first NMOS transistor in said pair of NMOS transistors is coupled to a terminal at which said signal is received by said slave circuit from said master circuit;
a drain terminal of a second NMOS transistor in said pair of NMOS transistors is coupled to an output terminal of said flip-flop and a gate terminal of said second NMOS transistor is provided with an inverted version of a clock signal;
a gate terminal of a first PMOS transistor in said pair of PMOS transistors is coupled to said terminal at which said signal is received by said slave circuit from said master circuit; and
a drain terminal of a second PMOS transistor in said pair of PMOS transistors is coupled to said output terminal and a gate of said second PMOS transistor is provided with said clock signal; and
generating a corresponding output signal at said output terminal based on said sensing of said signal.
2 . The method according to claim 1 , wherein a source terminal of said first NMOS transistor is coupled to ground and a source terminal of said first PMOS transistor is coupled to a high voltage.
3 . The method according to claim 1 , wherein said flip-flop comprises a SET input terminal for generating a high voltage signal at said output terminal.
4 . The method according to claim 3 , comprising:
receiving, in a feedback path of said master circuit, an inverted version of a SET signal from said SET input terminal; and
receiving, in a feedback path of said slave circuit, said SET signal from said SET input terminal.
5 . The method according to claim 3 , comprising receiving, in said master circuit, an inverted version of a SET signal from said SET input terminal via a gate terminal of a third PMOS transistor in said master circuit, wherein:
a drain terminal of said third PMOS transistor is coupled to a terminal between an output of an on-path transmission gate and an input of an on-path inverter in said master circuit; and
a source terminal of said third PMOS transistor is coupled to a high voltage.
6 . The method according to claim 3 , comprising controlling, in said input control circuit, enabling and disabling of an input terminal of said flip-flop utilizing a SET signal received from said SET input terminal.
7 . The method according to claim 1 , wherein said flip-flop comprises a RESET input terminal for generating a low voltage signal at said output terminal.
8 . The method according to claim 7 , comprising:
receiving, in a feedback path of said master circuit, a RESET signal from said RESET input terminal; and
receiving, in a feedback path of said slave circuit, an inverted version of said RESET signal from said RESET input terminal.
9 . The method according to claim 7 , comprising receiving, in said master circuit, a RESET signal from said RESET input terminal via a gate terminal of a third NMOS transistor in said master circuit, wherein:
a drain terminal of said third NMOS transistor is coupled to a terminal between an output of an on-path transmission gate and an input of an on-path inverter in said master circuit; and
a source terminal of said third NMOS transistor is coupled to ground.
10 . The method according to claim 7 , comprising controlling, in said input control circuit, enabling and disabling of an input terminal of said flip-flop utilizing a RESET signal received from said RESET input terminal.
11 . A system, comprising:
one or more circuits for use in a master-slave flip-flop, said one or more circuits comprising a master circuit, a slave circuit and an input control circuit, and said one or more circuits being operable to:
sense a signal received by said slave circuit from said master circuit at a pair of serially coupled NMOS transistors and/or at a pair of serially coupled PMOS transistors in said slave circuit, wherein:
a gate terminal of a first NMOS transistor in said pair of NMOS transistors is coupled to a terminal at which said signal is received by said slave circuit from said master circuit;
a drain terminal of a second NMOS transistor in said pair of NMOS transistors is coupled to an output terminal of said flip-flop and a gate terminal of said second NMOS transistor is provided with an inverted version of a clock signal;
a gate terminal of a first PMOS transistor in said pair of PMOS transistors is coupled to said terminal at which said signal is received by said slave circuit from said master circuit; and
a drain terminal of a second PMOS transistor in said pair of PMOS transistors is coupled to said output terminal and a gate of said second PMOS transistor is provided with said clock signal; and
generate a corresponding output signal at said output terminal based on said sensing of said signal.
12 . The system according to claim 11 , wherein a source terminal of said first NMOS transistor is coupled to ground and a source terminal of said first PMOS transistor is coupled to a high voltage.
13 . The system according to claim 11 , wherein said flip-flop comprises a SET input terminal for generating a high voltage signal at said output terminal.
14 . The system according to claim 13 , wherein said one or more circuits are operable to:
receive, in a feedback path of said master circuit, an inverted version of a SET signal from said SET input terminal; and
receive, in a feedback path of said slave circuit, said SET signal from said SET input terminal.
15 . The system according to claim 13 , wherein said one or more circuits are operable to receive, in said master circuit, an inverted version of a SET signal from said SET input terminal via a gate terminal of a third PMOS transistor in said master circuit, wherein:
a drain terminal of said third PMOS transistor is coupled to a terminal between an output of an on-path transmission gate and an input of an on-path inverter in said master circuit; and
a source terminal of said third PMOS transistor is coupled to a high voltage.
16 . The system according to claim 13 , wherein said one or more circuits are operable to control, in said input control circuit, enabling and disabling of an input terminal of said flip-flop utilizing a SET signal received from said SET input terminal.
17 . The system according to claim 11 , wherein said flip-flop comprises a RESET input terminal for generating a low voltage signal at said output terminal.
18 . The system according to claim 17 , wherein said one or more circuits are operable to:
receive, in a feedback path of said master circuit, a RESET signal from said RESET input terminal; and
receive, in a feedback path of said slave circuit, an inverted version of said RESET signal from said RESET input terminal.
19 . The system according to claim 17 , wherein said one or more circuits are operable to receive, in said master circuit, a RESET signal from said RESET input terminal via a gate terminal of a third NMOS transistor in said master circuit, wherein:
a drain terminal of said third NMOS transistor is coupled to a terminal between an output of an on-path transmission gate and an input of an on-path inverter in said master circuit; and
a source terminal of said third NMOS transistor is coupled to ground.
20 . The system according to claim 17 , wherein said one or more circuits are operable to control, in said input control circuit, enabling and disabling of an input terminal of said flip-flop utilizing a RESET signal received from said RESET input terminal.