IP Library Granted Patent US 9,128,853
Granted Patent B1
US 9,128,853 · App. 13/045,690 · Granted Sep 8, 2015

Lookup structure for large block cache

Inventors: Arvind Pruthi (Los Gatos, CA); Sandeep Karmarkar (Pune, IN); Kanishk Rastogi (Pune, IN)
Assignee: Toshiba Corporation
G06F12/0864
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Quick Facts
Patent No.
US 9,128,853
App. No.
13/045,690
Granted
Sep 8, 2015
Kind
B1
Abstract

Systems, methods, and other embodiments associated with a lookup structure for a large block cache are described. According to one embodiment, at least two blocks of data are stored in a cache. A lookup entry is constructed that describes the at least two blocks of data. The lookup entry includes block specific information that describes individual blocks of the at least two blocks of data. The lookup entry is stored in the lookup structure.

Claims (38)

1. An apparatus, comprising:

a metadata logic configured to construct one or more lookup entries that describes a range of more than one contiguous block of data stored in a cache; wherein the one or more lookup entries includes, in the same one or more lookup entries, i) block specific information that describes individual blocks of the range of more than one contiguous block of data and ii) common information common to the range of more than one contiguous block of data;

a lookup structure logic configured to store the one or more lookup entries in a hash table that includes one or more buckets, wherein

a storage access request is processed on the hash table to determine if requested data is stored in a cache,

the one or more buckets is configured to store the one or more lookup entries according to a hash function of, at least, cache offset information and a data store identifier,

the data store identifier identifying a particular data store from which the range of more than one contiguous block of data were transferred,

the common information includes at least one of LRU list information and the cache offset information, and

wherein each bucket has an associated collision list which includes the one or more lookup entries and the associated collision list lists cache mapping information corresponding to the data store identifier and the cache offset information.

2. The apparatus of claim 1 , wherein the one or more lookup entries includes a set of bits that identifies individual blocks of data that contain valid data.

3. The apparatus of claim 1 , wherein the one or more lookup entries includes a set of bits that identifies individual blocks of data that have been modified since being moved into the cache.

4. The apparatus of claim 1 , wherein the one or more lookup entries includes a set of bits that identifies a level of the cache in which the range of more than one contiguous block of data are stored.

5. The apparatus of claim 1 , wherein the lookup structure logic stores the one or more lookup entries as a single collision entry in the hash table.

6. The apparatus of claim 1 , wherein the metadata logic comprises processor-executable instructions stored on a non-transitory medium for constructing the one or more lookup entries.

7. The apparatus of claim 1 , wherein the lookup structure logic comprises processor-executable instructions stored on a non-transitory medium for storing the one or more lookup entries in the hash table.

8. The apparatus of claim 1 , wherein the common information further includes at least one of collision list information, a range block map, a range dirty map, or a range cache level map.

9. A method, comprising:

storing a range of more than one contiguous block of data;

constructing one or more lookup entries that describes the range of more than one contiguous block of data; and

further wherein the one or more lookup entries includes, in the same one or more lookup entries, i) block specific information that describes individual blocks of the range of more than one contiguous block of data and ii) collision list information common to the range of more than one contiguous block of data: and

storing the one or more lookup entries in a hash table that includes one or more buckets, wherein

a storage access request is processed on the hash table to determine if requested data is stored in a cache,

the one or more buckets is configured to store the one or more lookup entries according to a hash function of, at least, cache offset information and a data store identifier of the range of more than one contiguous block of data,

the one or more buckets further configured to point to an associated collision list and the associated collision list lists cache mapping information corresponding to the data store identifier and the cache offset information, and

the data store identifier identifying a particular data store from which the range of more than one contiguous block of data were transferred.

10. The method of claim 9 , comprising constructing the one or more lookup entries that includes a set of bits that identifies blocks of data that contain valid data.

11. The method of claim 9 , comprising constructing the one or more lookup entries that includes a set of bits that identifies individual blocks of data that have been modified since being moved into the cache.

12. The method of claim 9 , comprising constructing the one or more lookup entries that includes a set of bits that identifies a level of the cache in which the range of more than one contiguous block of data are stored.

13. An integrated circuit device, comprising:

a metadata logic configured to construct one or more lookup entries that describes a range of more than one contiguous block of data stored in a cache; and wherein the one or more lookup entries includes, in the same one or more lookup entries, i) block specific information that describes individual blocks of the range of more than one contiguous block of data and ii) cache offset information common to the range of more than one contiguous block of data, such that a same set of bits in the one or more lookup entries describe the range of more than one contiguous block of data;

a lookup structure logic configured to store the one or more lookup entries in a hash table that includes one or more buckets; and

storage media for storing the hash table,

wherein the lookup structure logic is further configured to process a storage access request on the hash table to determine if requested data is stored in a cache and, store the one or more lookup entries according to a hash function based, at least in part, on a data store identifier and a data store range offset of the range of more than one contiguous block of data, and

the data store identifier identifying a particular data store from which the range of more than one contiguous block of data were transferred, and

wherein the one or more buckets has an associated collision list and the associated collision list lists cache mapping information corresponding to the data store identifier and the data store range offset information.

14. The integrated circuit device of claim 13 , further comprising a lookup structure that includes a set of bits that identifies individual blocks of data that contain valid data.

15. The integrated circuit device of claim 13 , wherein the one or more lookup entries includes a set of bits that identifies individual blocks of data that have been modified since being moved into the cache.

16. The integrated circuit device of claim 13 , wherein the one or more lookup entries includes a set of bits that identifies a level of the cache in which the range of more than one contiguous block of data are stored.

17. The integrated circuit device of claim 13 , wherein the lookup structure logic is configured to store the one or more lookup entries as a single entry in the hash table.

Assignments (9)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2018
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 047262/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2014
From: MARVELL INTERNATIONAL LTD.
To: TOSHIBA CORPORATION
Reel/Frame 032208/0241 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: KARMARKAR, SANDEEP; RASTOGI, KANISHK
To: MARVELL INDIA PVT. LTD.
Reel/Frame 025953/0878 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: MARVELL INDIA PVT. LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025953/0894 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025953/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: PRUTHI, ARVIND
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 025953/0509 →
Continuity (1)
Provisional Application 61331761 · May 5, 2010