Method of manufacturing semiconductor circuit device
View Patent ↗Provided is a method of manufacturing a semiconductor circuit device including a MOS transistor and a capacitor element in which a gate electrode of a MOS transistor is formed of a first polysilicon film, a capacitor is formed of the first polysilicon film, a capacitor film, and a second polysilicon film, reduction in resistance of a normally-off transistor and reduction in resistance of a lower electrode of the capacitor are simultaneously performed, and reduction in resistance of an N-type MOS transistor and reduction in resistance of an upper electrode of the capacitor are simultaneously performed.
1. A method of manufacturing a semiconductor circuit device including an NMOS and a PMOS transistor, an EDS protection device, and a capacitor element, the method comprising:
selectively forming a LOCOS film on a semiconductor substrate to form an active region;
forming a gate insulating film on a surface of the active region;
forming a first polysilicon film on the gate insulating film and the LOCOS film;
patterning the first polysilicon film to form a lower electrode of the capacitor element and gate electrodes of the NMOS transistor, the PMOS transistor, and a gate electrode of the ESD protection device;
after forming the lower electrode and the gate electrodes, implanting high concentration N-type impurities into a region for the ESD protection device which is not of an LDD type and the lower electrode of the capacitor element at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 ,
wherein the gate electrode of the ESD protection device comprises a first resistance element having a first electrical resistance and the upper electrode of the capacitor element comprises a second resistance element having a second electrical resistance that is higher than the first electrical resistance;
implanting N-type impurities into a region for the NMOS transistor which is of an LDD type to form N-type LDD regions, and implanting P-type impurities into a region for the PMOS transistor which is of the LDD type to form P-type LDD regions;
forming a capacitor film;
forming a second polysilicon film on the capacitor film;
patterning the second polysilicon film to form an upper electrode of the capacitor element and a resistor element;
implanting N-type impurities at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 to form N-type source and drain regions, an N-type polysilicon gate electrode, an N-type upper electrode of the capacitor, and an N-type contact region; and
implanting P-type impurities at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 to form P-type source and drain regions, a P-type polysilicon gate electrode, an P-type upper electrode of the capacitor, and a P-type contact region.
2. A method of manufacturing a semiconductor circuit device according to claim 1 , further comprising forming side walls after the implanting N-type impurities to form the N-type LDD regions and the implanting P-type impurities to form the P-type LDD regions.
3. A method of manufacturing a semiconductor circuit device according to claim 1 , wherein the second polysilicon film is formed thinner than the first polysilicon film.
4. A method of manufacturing a semiconductor circuit device according to claim 1 , wherein the second resistance element has a contact region which is different in impurity concentration with respect to the first resistance element.
5. A method of manufacturing a semiconductor circuit device according to claim 1 , wherein the MOS transistor which is of the LDD type is formed without side walls, and a length of LDD regions is determined by a photomask.
6. A method of manufacturing a semiconductor circuit device according to claim 1 , further comprising performing thermal treatment between the implanting high concentration N-type impurities at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 and the implanting high concentration P-type impurities at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 .