Thin-film transistor, method of fabricating the thin-film transistor, and display substrate using the thin-film transistor
View Patent ↗Provided is an oxide thin-film transistor (TFT) substrate that may enhance the display quality of a display device and a method of fabricating the same via a simple process. The oxide TFT substrate includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.
1. An oxide thin-film transistor (TFT) substrate, comprising:
a substrate;
a gate line disposed on the substrate;
a data line disposed on the substrate and insulated from and intersecting the gate line;
an oxide TFT electrically connected to the gate line and the data line; and
a pixel electrode electrically connected to the oxide TFT,
wherein an oxide layer of the oxide TFT comprises:
a first region with semiconductor characteristics and comprising a channel; and
a second region that is conductive and surrounds the first region,
wherein the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.
2. The oxide TFT substrate of claim 1 , further comprising:
a first passivation film disposed on the oxide layer and comprising a first hole exposing the first region; and
a second passivation film disposed on the first passivation film and comprising a second hole exposing the first hole and the first region,
wherein the pixel electrode is disposed on the second passivation film and contacts the first region through the first hole and the second hole.
3. The oxide TFT substrate of claim 2 , wherein the first passivation film and the second passivation film comprise different materials from each other.
4. The oxide TFT substrate of claim 3 , wherein the first passivation film comprises silicon oxide (SiOx), and the second passivation film comprises silicon nitride (SiNx).
5. The oxide TFT substrate of claim 2 , wherein the first passivation film and the second passivation film comprise the same material.
6. The oxide TFT substrate of claim 5 , wherein the first passivation film and the second passivation film comprise silicon oxide (SiOx).
7. The oxide TFT substrate of claim 2 , wherein the number of first holes is greater than one, and the number of second holes is greater than one.
8. The oxide TFT substrate of claim 2 , wherein the oxide layer comprises an amorphous oxide comprising at least one of indium (In), zinc (Zn), gallium (Ga), hafnium (Hf), or any combination thereof.
9. The oxide TFT substrate of claim 8 , wherein the amorphous oxide comprises In, Zn, and Ga.
10. The oxide TFT substrate of claim 8 , wherein the amorphous oxide comprises In, Zn, and Hf.
11. An oxide thin-film transistor (TFT) substrate, comprising:
a substrate;
a gate line disposed on the substrate;
a data line disposed on the substrate and insulated from and intersecting the gate line;
an oxide TFT electrically connected to the gate line and the data line; and
a pixel electrode electrically connected on the oxide TFT,
wherein the oxide TFT comprises:
a gate electrode connected to the gate line;
a gate insulating film disposed on the gate line and the gate electrode;
an oxide layer disposed on the gate insulating film and overlapping the gate electrode;
a first passivation film disposed on the oxide layer and partially overlapping the oxide layer; and
a source electrode connected to the data line and partially overlapping the oxide layer,
wherein the oxide layer comprises:
a first region with semiconductor characteristics and comprising a channel; and
a second region that is conductive and surrounds the first region,
wherein the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.
12. The oxide TFT substrate of claim 11 , further comprising a second passivation film disposed between the oxide TFT and the pixel electrode, wherein the pixel electrode contacts the first region through a first hole in the first passivation film that exposes the first region and a second hole in the second passivation film that exposes the first hole and the first region.
13. The oxide TFT substrate of claim 12 , wherein the first passivation film and the second passivation film comprise different materials from each other.
14. The oxide TFT substrate of claim 13 , wherein the first passivation film comprises silicon oxide (SiOx), and the second passivation film comprises silicon nitride (SiNx).
15. The oxide TFT substrate of claim 12 , wherein the first passivation film and the second passivation film comprise the same material.
16. The oxide TFT substrate of claim 15 , wherein the first passivation film and the second passivation film comprise silicon oxide (SiOx).
17. The oxide TFT substrate of claim 12 , wherein the number of first holes is greater than one, and the number of second holes is greater than one.
18. The oxide TFT substrate of claim 12 , wherein the oxide layer comprises an amorphous oxide comprising at least one of indium (In), zinc (Zn), gallium (Ga), hafnium (Hf), or any combination thereof.
19. The oxide TFT substrate of claim 18 , wherein the amorphous oxide comprises In, Zn, and Ga.
20. The oxide TFT substrate of claim 18 , wherein the amorphous oxide comprises In, Zn, and Hf.
21. The oxide TFT substrate of claim 1 , wherein the second region is contiguous.
22. The oxide TFT substrate of claim 1 , wherein the second region completely surrounds the first region.
23. The oxide TFT substrate of claim 11 , wherein the second region is contiguous.
24. The oxide TFT substrate of claim 11 , wherein the second region completely surrounds the first region.
25. The oxide TFT substrate of claim 1 , wherein pixel electrode physically contacts the first region.
26. The oxide TFT substrate of claim 11 , wherein pixel electrode physically contacts the first region.