IP Library Patent Application 13046171
Patent Application
App. No. 13/046,171

LINE-REFLECT-REFLECT MATCH CALIBRATION

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Quick Facts
Patent No.
US None
App. No.
13/046,171
Abstract

A method of compensating a calibration for a vector network analyzer includes performing calibrations on at least a pair of ports to determine error terms associated with each port wherein at least one of the error terms is based upon selecting the reactance of the load standard from a set of potential values in a manner such that the reference reactance errors are reduced.

Claims (8)

1 . A method of compensating a calibration for a vector network analyzer comprising:

(a) performing calibrations on at least a pair of ports to determine error terms associated with each port;

(b) wherein at least one of said error terms is based upon selecting the reactance of the load standard from a set of potential values in a manner such that the reference reactance errors are reduced.

2 . The method of claim 1 wherein said method accounts for differences between the load measured at a probe-tip reference plane and measured at a center-of-thru reference plane.

3 . The method of claim 1 wherein said set of potential value is based upon said reactance of said load.

4 . The method of claim 1 wherein for each of said potential values computing a load impedance at the probe tip.

5 . The method of claim 4 wherein for each said computed load impedance at said probe tip translating to the thru-center reference place.

6 . The method of claim 5 wherein at least one error term is renormalized based upon said translated computed load impedance.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: HAYDEN, LEONARD A
To: CASCADE MICROTECH, INC.
Reel/Frame 025963/0058 →