Thin film transistor, and method of manufacturing the same
View Patent ↗A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a first gate electrode and an active layer including a crystalline oxide semiconductor which is insulated from the first gate electrode by a first insulating layer and the active layer is arranged to overlap the first gate electrode. A source electrode is formed including at least a portion overlaps the active layer, and a drain electrode is arranged being spaced apart from the source electrode and at least a portion of the drain electrode overlaps the active layer, wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer.
1. A thin film transistor, comprising:
a first gate electrode;
an active layer comprising a crystalline oxide semiconductor layer being insulated from the first gate electrode by a first insulating layer, the active layer being arranged to overlap the first gate electrode;
a source electrode and a drain electrode spaced apart from the source electrode;
a second insulating layer; and
a second gate electrode, the second gate electrode and the first gate electrode being arranged on opposite sides of the active layer,
wherein the second gate electrode is insulated from the active layer by the second insulating layer,
wherein the active layer comprises a triple layer comprising a first crystalline oxide semiconductor layer, an amorphous oxide semiconductor layer, and a second crystalline oxide semiconductor layer, and
wherein the first crystalline oxide semiconductor layer is arranged adjacent to the first insulating layer, and the second crystalline oxide semiconductor layer is arranged adjacent to the second insulating layer.
2. The thin film transistor of claim 1 , wherein the active layer comprises a single layer of the crystalline oxide semiconductor.
3. The thin film transistor of claim 1 , wherein the active layer comprises a double layer comprising an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer are laminated, and the crystalline oxide semiconductor layer is arranged adjacent to the first insulating layer.
4. The thin film transistor of claim 3 , wherein the thickness of the amorphous oxide semiconductor layer exceeds the thickness of the crystalline oxide semiconductor layer.
5. The thin film transistor of claim 1 , wherein the thickness of the amorphous oxide semiconductor layer exceeds the thickness of the first crystalline oxide semiconductor layer or the thickness of the second crystalline oxide semiconductor layer.
6. The thin film transistor of claim 1 , wherein the crystalline oxide semiconductor comprises an oxide material selected from one of Zn, In, Ga, Sn, Hf, or any combinations thereof.
7. The thin film transistor of claim 1 , wherein an energy band gap of the crystalline oxide semiconductor exceeds an energy band gap of an amorphous oxide semiconductor.
8. The thin film transistor of claim 1 , wherein a light absorption coefficient of the crystalline oxide semiconductor is smaller than a light absorption coefficient of an amorphous oxide semiconductor.
9. The thin film transistor of claim 1 , wherein a charge mobility of the crystalline oxide semiconductor is lower than a charge mobility of an amorphous oxide semiconductor.
10. The thin film transistor of claim 1 , wherein the degree of variation of a threshold voltage by light irradiation onto the crystalline oxide semiconductor is lower than the degree of variation of a threshold voltage by light irradiation onto an amorphous oxide semiconductor.
11. The thin film transistor of claim 1 , wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer, and wherein at least a portion of the source electrode overlaps with the active layer, and at least a portion of the drain electrode overlaps with the active layer.
12. A thin film transistor, comprising:
a first gate electrode;
an active layer comprising a crystalline oxide semiconductor and an amorphous oxide semiconductor sequentially being disposed on the active layer and being insulated from the first gate electrode by a first insulating layer, the active layer being arranged to overlap the first gate electrode;
a source electrode and a drain electrode spaced apart from the source electrode;
a second insulating layer; and
a second gate electrode, the second gate electrode and the first gate electrode being arranged on opposite sides of the active layer,
wherein the second gate electrode is insulated from the active layer by the second insulating layer,
wherein the active layer comprises a triple layer comprising a first crystalline oxide semiconductor layer, an amorphous oxide semiconductor layer, and a second crystalline oxide semiconductor layer, and
wherein the first crystalline oxide semiconductor layer is arranged adjacent to the first insulating layer, and the second crystalline oxide semiconductor layer is arranged adjacent to the second insulating layer.