IP Library Granted Patent US 9,154,160
Granted Patent B2
US 9,154,160 · App. 13/049,798 · Granted Oct 6, 2015

Capacitance to code converter with sigma-delta modulator

Inventor: Viktor Kremin (Lviv, UA)
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
H03M11/02G06F3/044
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Quick Facts
Patent No.
US 9,154,160
App. No.
13/049,798
Granted
Oct 6, 2015
Kind
B2
Abstract

An apparatus and method of converting a capacitance measured on a sensor element to a digital value. The apparatus may include a switching capacitor as a sensor element, a modulation circuit coupled to the sensor element, and a switching circuit having a plurality of switches controlled by a variable-period clock. The modulation circuit is configured to measure a capacitance on the sense element and to convert the measured capacitance to a digital value.

Claims (42)

1. A method, comprising:

measuring a mutual capacitance on a sense element of a sensing device using a modulation circuit, wherein the sensing device comprises a plurality of drive lines and a plurality of sense lines, and wherein the sense element comprises an intersection between one drive line of the plurality of drive lines and one sense line of the plurality of sense lines, and wherein the sense element is representative of a capacitor, and wherein the measuring the mutual capacitance on the sense element comprises:

applying a drive signal to the one drive line using an excitation signal source; and

sensing, by the modulation circuit, the drive signal on the one sense line to measure the mutual capacitance of the capacitor;

switching the capacitor to be coupled and decoupled to a modulator capacitor of the modulation circuit using a plurality of switches, wherein the plurality of switches is controlled by a spread spectrum clock; and

converting the mutual capacitance measured on the sense element to a digital value.

2. The method of claim 1 , wherein the measuring the mutual capacitance on the sense element further comprises:

charging the mutual capacitance on the sense element on the one drive line coupled to a first node of the capacitor during a first phase of the plurality of switches; and

measuring the charging of the mutual capacitance on the sense element on the one sense line coupled to a second node of the capacitor using the modulation circuit during a second phase of the plurality of switches.

3. The method of claim 2 , wherein the switching comprises:

coupling a voltage source to the first node of the capacitor using a first one of the plurality of switches for the charging of the mutual capacitance on the sense element during the first phase; and

coupling the first node of the capacitor to a first node of the modulator capacitor during the second phase.

4. The method of claim 2 , wherein the switching comprises:

coupling a voltage source to the first node of the capacitor using a first one of the plurality of switches for the charging of the mutual capacitance on the sense element during the first phase; and

alternately coupling the first node of the capacitor and a discharge resistor to a first node of the modulator capacitor of the modulation circuit.

5. The method of claim 2 , wherein the measuring the mutual capacitance on the sense element further comprises discharging a voltage on the modulator capacitor when the voltage on the modulator capacitor reaches a reference voltage.

6. The method of claim 5 , wherein the discharging the voltage on the modulator capacitor comprises connecting a discharge resistor between a first node of the modulator capacitor and ground using a third switch of the plurality of switches controlled by an output signal of a comparator, wherein the comparator toggles the output signal when the voltage on the modulator capacitor crosses the reference voltage.

7. The method of claim 1 , wherein the switching comprises switching the capacitor between a voltage source and a first node of the modulator capacitor of the modulation circuit using the plurality of switches.

8. The method of claim 1 , wherein the digital value is commensurate to the measured mutual capacitance on the sense element.

9. An apparatus comprising:

a sensing device comprising a plurality of drive lines and a plurality of sense lines to form a plurality of sense elements, wherein the plurality of sense elements comprises intersections between the plurality of drive lines and the plurality of sense lines, wherein the plurality of sense elements is represented as capacitors;

an excitation signal source to provide a drive signal;

a modulation circuit to be selectively coupled to one or more of the plurality of sense elements; and

a switching circuit having a plurality of switches controlled by a variable-period clock, wherein the modulation circuit is to measure mutual capacitances of the plurality of sense elements using the plurality of switches, and wherein the modulation circuit is to convert the measured mutual capacitances to digital values, wherein the modulation circuit is to measure one or more of the mutual capacitances of the one or more of one of the plurality of sense elements by applying the drive signal to a respective one of the plurality of drive lines and sensing the drive signal on a corresponding one of the plurality of sense lines.

10. The apparatus of claim 9 , further comprising a circuit to provide at least one of a pseudo-random clock or a dithered clock as the variable-period clock to control the switching circuit.

11. The apparatus of claim 9 , further comprising:

an oscillator to provide an oscillator signal; and

a pseudo-random signal (PRS) circuit, comprising a PRS generator to receive the oscillator signal and to generate a PRS as the variable-period clock to control the switching circuit.

12. The apparatus of claim 11 , wherein the PRS circuit further comprises a PRS counter.

13. The apparatus of claim 9 , further comprising a voltage-controlled oscillator (VCO) to provide the variable-period clock to control the switching circuit.

14. The apparatus of claim 9 , further comprising a spread-spectrum clock circuit to provide the variable-period clock to control the switching circuit.

15. The apparatus of claim 9 , wherein a first switch of the plurality of switches is coupled between a voltage source and a first node of one capacitor of the capacitors and a second switch of the plurality of switches is coupled between the first node of the capacitor and a first node of a modulator capacitor of the modulation circuit, wherein the switching circuit is to provide a charge current to the capacitor in a first phase using the first switch of the plurality of switches and to transfer the charge current on the one capacitor, accumulated during the first phase, to the modulator capacitor during a second phase using the second switch of the plurality of switches.

16. The apparatus of claim 9 , wherein the modulation circuit comprises a sigma-delta modulator.

17. The apparatus of claim 9 , further comprising one or more digital filters coupled to receive an output of the modulation circuit, wherein the output of the modulation circuit is a digital output bitstream, and wherein the one or more digital filters are to convert the digital output bitstream into one digital value of the digital values.

18. A system comprising:

a capacitance sense array comprising a plurality of sense elements, wherein each of the plurality of sense elements comprises intersections between a plurality of drive lines and a plurality of sense lines, wherein the plurality of sense elements is representative of switching capacitors; and

a processing device coupled to the capacitance sense array, the processing device comprising:

an excitation signal source to provide a drive signal;

a switching circuit having a plurality of switches, wherein the processing device is to control the plurality of switches using a variable-period clock; and

a modulation circuit to be coupled to one of the plurality of sense elements, wherein the modulation circuit is to measure a mutual capacitance on the one of the plurality of sense elements using the plurality of switches, and wherein the modulation circuit is to convert the measured mutual capacitance to a digital value.

19. The system of claim 18 , wherein the processing device further comprises a pseudo-random signal (PRS) circuit coupled to the switching circuit and the modulation circuit, wherein the PRS circuit is to provide a PRS as the variable-period clock to control the switching circuit.

20. The system of claim 18 , wherein the modulation circuit is a capacitance-to-duty-cycle converter, wherein a modulator duty cycle of the modulation circuit changes when a presence of a conductive object is detected on the one of the plurality of sense elements.

Assignments (7)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
PATENT SECURITY AGREEMENT Recorded Aug 28, 2012
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 028863/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2011
From: KREMIN, VIKTOR
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 025971/0096 →
Continuity (1)
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