Core-shell-shell nanowire transistor
A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure. The source/drain (S/D) regions in end sections of the CS nanostructure flanking are doped.
1. A core-shell-shell (CSS) nanowire transistor (NWT), the NWT comprising:
a substrate with a surface;
a cylindrical CSS nanostructure with a semiconductor core, an insulator shell surrounding the semiconductor core, and a conductive shell surrounding the insulator shell, the CSS nanostructure having a lower hemicylinder overlying the substrate surface;
a gate electrode formed from the conductive shell in a center section of the CSS nanostructure;
insulating reentrant stringers located between the substrate surface and the CSS nanostructure lower hemicylinder in the center section;
a conductive film gate strap overlying the gate electrode and the reentrant stringers in the center section of the CSS nanostructure;
source/drain (S/D) regions formed in exposed regions of the semiconductor core, in end sections of the CSS nanostructure.
2. The NWT of claim 1 further comprising:
a channel formed in the semiconductor core in the center section of the CSS nanostructure underlying the gate electrode; and,
lightly doped drain (LDD) regions formed in exposed regions the semiconductor core between the S/D regions and the channel.
3. The NWT of claim 2 wherein each LDD region has a width of less than 2 micrometers.
4. The NWT of claim 1 wherein the reentrant stringers are a material selected from a group consisting of oxide and nitride.
5. The NWT of claim 1 wherein the semiconductor core is single-crystal Si, the insulator shell a Si-containing material, and the conductive shell a metal-containing material.
6. The NWT of claim 1 wherein the conductive film gate strap is a material selected from a group consisting of doped amorphous silicon (a-Si), tungsten (W), and tungsten nitride (WN).
7. The NWT of claim 1 wherein the conductive film gate strap is a doped a-Si having a thickness in a range of about 50 to 200 nanometers (nm).
8. The NWT of claim 1 wherein the semiconductor core material is selected from a group consisting of silicon (Si), germanium (Ge), carbon-nanotubes, Group III-IV compounds, and Group II-VI compounds.