IP Library Granted Patent US 8,584,961
Granted Patent B2
US 8,584,961 · App. 13/051,529 · Granted Nov 19, 2013

Marking verification system

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Quick Facts
Patent No.
US 8,584,961
App. No.
13/051,529
Granted
Nov 19, 2013
Kind
B2
Abstract

A marking system and related methods are disclosed in which a micromark having optically readable characteristics and electronically readable characteristics is made on a selected object. The optically and electronically readable characteristics of the micromark contain corresponding data. Preferred embodiments of the invention include non-volatile memory for storing duplicate data.

Claims (33)

1. A marking system comprising:

a micromark having optically readable characteristics and electronically readable characteristics, wherein the optically and electronically readable characteristics contain corresponding data and reside on the same object, the micromark including a plurality of two-state cells arranged in a two-dimensional array with a plurality of rows and a plurality of columns, each cell including a fuse and a circuit configured to set the state and read the state, the cells positioned such that, within a row, all of the fuses are aligned and all of the circuits are aligned.

2. The marking system according to claim 1 , wherein the wherein the micromark further comprises nonvolatile memory cells.

3. The marking system according to claim 1 , wherein the micromark further comprises fuses.

4. The marking system according to claim l wherein the micromark further comprises metallic fuses.

5. The marking system according to claim 1 , wherein the micromark further comprises poly-silicon fuses.

6. The marking system according to claim 1 , wherein the micromark further comprises zener zaps.

7. The marking system according to claim 1 , wherein the micromark further comprises gate oxide rupture structures.

8. The marking system according to claim 1 , wherein the micromark further comprises encrypted data.

9. The marking system according to claim 1 , wherein the micromark resides on a semiconductor wafer.

10. The marking system according to claim 1 , wherein the micromark resides on a semiconductor device.

11. The marking system according to claim 1 , wherein the micromark resides on currency.

12. The marking system according to claim 1 , wherein the micromark resides on a pharmaceutical product.

13. The marking system according to claim 1 , wherein the micromark resides on a consumer product.

14. The marking system according to claim 1 , wherein the micromark resides on a unique object.

15. A marking method comprising the steps of:

inscribing a micromark on an object, the micromark having optically readable characteristics and electronically readable characteristics, wherein the optically and electronically readable characteristics contain corresponding information, the micromark including a plurality of two-state cells arranged in a two-dimensional array with a plurality of rows and a plurality of columns, each cell including a fuse and a circuit configured to set the state and read the state, the cells positioned such that, within a row, all of the fuses are aligned and all of the circuits are aligned.

16. The marking method according to claim 15 , further comprising the step of verifying the data content of the micromark.

17. The marking method according to claim 15 , further comprising the step of encrypting the data content of the micromark.

18. The marking method according to claim 15 , wherein the step of inscribing a micromark on an object further comprises forming an open circuit in an electrical element.

19. The marking method according to claim 15 , wherein the step of inscribing a micromark on an object further comprises forming a closed circuit in an electrical element.

20. The marking method according to claim 15 , wherein the step of inscribing a micromark on an object further comprises laser machining a surface.

21. The marking method according to claim 15 , wherein the step of inscribing a micromark on an object further comprises chemically etching a surface.

22. The marking method according to claim 15 , wherein the step of inscribing a micromark on an object further comprises altering a surface material by applying electric current.

23. The marking method according to claim 15 , further comprising the step of storing duplicate micromark data in a database.

24. A micromark comprising:

a matrix comprising optically readable features and electronically readable non-volatile memory; whereby data stored in the matrix may be read optically and electronically, the matrix including a plurality of two-state cells arranged in a two-dimensional array with a plurality of rows and a plurality of columns, each cell including a fuse and a circuit configured to set the state and read the state, the cells positioned such that, within a row, all of the fuses are aligned and all of the circuits are aligned.

25. A micromark according to claim 24 wherein the optically readable features and electronically readable non-volatile memory store identical data.

26. A micromark according to claim 24 wherein one optically readable feature and one electronically readable non-volatile memory cell are implemented in one unitary physical element.

27. A semiconductor die with integrated circuitry and a plurality of perimeter-positioned wire bond pads, the semiconductor die comprising:

a micromark having optically readable characteristics and electronically readable characteristics, wherein the optically and electronically readable characteristics contain corresponding data and are collocated, the micromark being positioned at a perimeter of the die in alignment with the wire bond pads; and

a micromark access circuit separated on the die from the micromark and the integrated circuitry, the micromark access circuit configured to electronically read the micromark.

28. The semiconductor die of claim 27 , wherein the micromark includes a plurality of two-state cells arranged in a two-dimensional array with a plurality of rows and a plurality of columns, each cell including a fuse and a circuit configured to set the state and read the state, the cells positioned such that, within a row, all of the fuses are aligned and all of the circuits are aligned.

Assignments (4)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (040646/0799) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0544 →
SECURITY INTEREST Recorded Nov 17, 2016
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 040646/0799 →
SECURITY INTEREST Recorded May 28, 2015
From: TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 035732/0326 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2011
From: CHEN, WAYNE; TEGGATZ, ROSS
To: TRIUNE IP LLC
Reel/Frame 026280/0352 →