Dark current reduction in image sensors via dynamic electrical biasing
In various embodiments, an image sensor and method of using an image sensor are described. In an example embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions with each pixel region comprising an optically sensitive material over the substrate and positioned to receive light. There is a bias electrode for each pixel region, with the bias electrode configured to provide a bias voltage to the optically sensitive material of the respective pixel region. Also included is a pixel circuit for each pixel region with each pixel circuit comprising a charge store formed on the semiconductor substrate and a read out circuit, the charge store being in electrical communication with the optically sensitive material of the respective pixel region. The pixel circuit is configured to reset the voltage on the charge store to a reset voltage during a reset period, to integrate charge from the optically sensitive material to the charge store during an integration period, and to read out a signal from the charge store during a read out period. The pixel circuit includes a reference voltage node to be coupled to the charge store during the reset period and the read out circuit during the read out period where a reference voltage is applied to the reference voltage node and is configured to be varied during the operation of the pixel circuit.
1. An image sensor comprising:
a semiconductor substrate;
a plurality of pixel regions, each of the plurality of pixel regions comprising an optically sensitive material over the substrate, the optically sensitive material positioned to receive light;
a bias electrode for each of the plurality of pixel regions, the bias electrode configured to provide a bias voltage to the optically sensitive material of the respective pixel region;
a pixel circuit for each of the plurality of pixel regions, each pixel circuit comprising a charge store formed on the semiconductor substrate and a read out circuit, the charge store in electrical communication with the optically sensitive material of the respective pixel region, the charge store being a diode that is characterized by a leakage current;
the pixel circuit configured to reset the voltage on the charge store to a reset voltage during a reset period;
the pixel circuit configured to discharge charge from the charge store to the optically sensitive material during an integration period; and
the pixel circuit configured to read out a signal from the charge store during a read out period;
wherein the bias voltage is configured to change from a first level during the reset period to a second level during the integration period;
wherein the bias voltage is configured to change from the second level during the integration period to a third level during the read out period; and
wherein the choice of the second level bias voltage during the integration period is to lead to a lower charge store leakage current during the integration period compared to during the reset period.
2. The image sensor of claim 1 , wherein the first level of the bias voltage is to be greater than the second level of the bias voltage.
3. The image sensor of claim 1 , wherein the third level of the bias voltage is to be greater than the second level of the bias voltage.
4. The image sensor of claim 1 , wherein the third level of the bias voltage is to be equal to the first level of the bias voltage.
5. The image sensor of claim 1 , wherein the third level of the bias voltage is to be less than 2 volts.
6. The image sensor of claim 1 , wherein the third level of the bias voltage is to be about 0 volts.
7. The image sensor of claim 1 , wherein the first level of the bias voltage is to be lower than the reset voltage.
8. The image sensor of claim 1 , wherein the voltage of the charge store is configured to be reduced from the reset voltage to a lower starting voltage for integration.
9. The image sensor of claim 8 , wherein the starting voltage of the charge store for integration is to be less than 3 volt.
10. The image sensor of claim 8 , wherein the starting voltage of the charge store for integration is less than 2 volt.
11. The image sensor of claim 8 , wherein the starting voltage of the charge store for integration is to be less than 1 volt.
12. The image sensor of claim 1 , wherein the voltage of the charge store is configured to be increased during the read out period for read out.
13. The image sensor of claim 1 , wherein the first level of the bias voltage is to be less than 2 volts.
14. The image sensor of claim 1 , wherein the first level of the bias voltage is to be less than 1 volts.
15. The image sensor of claim 1 , wherein the first level of the bias voltage is to be about 0 volts.
16. The image sensor of claim 1 , wherein the second level of the bias voltage is to be less than 0 volts.
17. The image sensor of claim 1 , wherein the second level of the bias voltage is to be less than −1 volts.
18. The image sensor of claim 1 , wherein the second level of the bias voltage is to be 2 volts or less.
19. The image sensor of claim 1 , wherein reset voltage is to be greater than 1 volt.
20. The image sensor of claim 1 , wherein the reset voltage is to be greater than 2 volts.
21. The image sensor of claim 1 , wherein the reset voltage is to be greater than 3 volts.
22. The image sensor of claim 1 , wherein the reset voltage is to be less than 5 volts.
23. The image sensor of claim 1 , wherein the reset voltage is to be less than 3 volts.
24. The image sensor of claim 1 , wherein the voltage of the charge store is configured to decrease during the integration period.
25. The image sensor of claim 1 , wherein the bias voltage and the pixel circuit are configured to cause the voltage of the charge store to decrease by 3 volts or less during the integration period.
26. The image sensor of claim 1 , wherein the pixel circuit is configured to perform correlated double sampling during the read out period.
27. The image sensor of claim 1 , wherein the charge store comprises a diode formed in the semiconductor substrate.
28. The image sensor of claim 1 , further comprising a pixel electrode between the optically sensitive material and the charge store.
29. The image sensor of claim 28 , wherein the pixel circuit is configured to vary the voltage of the pixel electrode relative to a substrate potential of the semiconductor substrate during the operation of the pixel circuit.
30. The image sensor of claim 28 , wherein the bias voltage and the voltage of the pixel electrode are configured to be varied relative to a substrate potential of the semiconductor substrate independently of one another during the operation of the pixel circuit.
31. The image sensor of claim 1 , wherein the bias voltage is configured to be varied relative to a substrate potential of the semiconductor substrate during the operation of the pixel circuit.
32. The image sensor of claim 1 , wherein the bias electrode is a common electrode for the plurality of pixel regions.
33. A method of detecting an image, the method comprising:
resetting the voltage of a charge store to a reset voltage during a reset period;
applying a bias voltage across an optically sensitive material during an integration period;
varying the charge on the charge store during the integration period based on the intensity of light incident on the optically sensitive material during the integration period, the charge store being a diode that is characterized by a leakage current;
reading out a signal from the charge store during a read out period;
changing the bias voltage from a first level during the reset period to a second level during the integration period, the choice of the second level bias voltage during the integration period leading to a lower charge store leakage current during the integration period compared to during the reset period; and
changing the bias voltage from the second level during the integration period to a third level during the read out period.
34. The method of claim 33 , wherein further comprising selecting the charge store to comprise a diode formed in a semiconductor substrate.
35. The method of claim 33 , wherein the first level of the bias voltage is greater than the second level of the bias voltage.
36. The method of claim 33 , wherein the third level of the bias voltage is greater than the second level of the bias voltage.
37. The image sensor of claim 33 , wherein the third level of the bias voltage is equal to the first level of the bias voltage.
38. The method of claim 33 , wherein the first level of the bias voltage is lower than the reset voltage.
39. The method of claim 33 , further comprising reducing the voltage of the charge store from the reset voltage to a lower starting voltage for integration.
40. The method of claim 33 , further comprising increasing the voltage of the charge store during the read out period for read out.
41. The method of claim 33 , wherein the voltage of the charge store decreases during the integration period.