III-nitride transistor stacked with FET in a package
View Patent ↗One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
1. A three-terminal stacked-die package comprising:
a field effect transistor (FET) stacked on a top surface of a III-nitride transistor, such that a drain of said FET resides on and is electrically coupled to a source of said III-nitride transistor;
a first terminal coupled to a gate of said FET;
a second terminal coupled to a drain of said III-nitride transistor;
a third terminal coupled to a source of said FET, said source of said FET is disposed on a surface opposite said drain of said FET, and said source of said FET is coupled to a gate of said III-nitride transistor on said top surface.
2. The stacked-die package of claim 1 , wherein a said III-nitride transistor and said FET, form a cascoded switch.
3. The stacked-die package of claim 1 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a ribbon.
4. The stacked-die package of claim 1 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a clip.
5. The stacked-die package of claim 1 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a wirebond.
6. The stacked-die package of claim 1 , wherein said FET is a silicon FET.
7. The stacked-die package of claim 1 , wherein said III-nitride transistor is selected from the group consisting of a GaN FET and a GaN HEMT.
8. The stacked-die package of claim 1 , wherein each of said first terminal, second terminal, and third terminal is coupled to respectively a first lead, a second lead, and a third lead of said stacked-die package.
9. The stacked-die package of claim 1 , wherein said stacked-die package is a leadless package.
10. The stacked-die package of claim 1 , wherein said III-nitride transistor comprises a depletion-mode GaN.
11. A three-terminal semiconductor package comprising:
a field effect transistor (FET);
a III-nitride transistor;
a first terminal of said package coupled to a gate of said PET;
a second terminal of said package coupled to a drain of said III-nitride transistor;
a third terminal of said package coupled to a source of said FET, said source of said FET is coupled to a gate of said III-nitride transistor on a top surface of said III-nitride transistor and said source of said FET is disposed above a drain of said FET;
wherein said drain of said FET is disposed on said to surface of said III-nitride transistor such that said drain of said FET is mechanically and electrically coupled to a source of said III-nitride transistor by direct attachment without using wire bonding.
12. The semiconductor package of claim 11 , wherein said III-nitride transistor and said FET form a cascoded switch.
13. The semiconductor package of claim 11 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a ribbon.
14. The semiconductor package of claim 11 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a clip.
15. The semiconductor package of claim 11 , wherein said gate of said III-nitride transistor is coupled to said source of said FET by a wirebond.
16. The semiconductor package of claim 11 , wherein said FET is a silicon FET.
17. The semiconductor package of claim 11 , wherein said III-nitride transistor is selected from the group consisting of a GaN FET and a GaN HEMT.
18. The semiconductor package of claim 11 , wherein each of said first terminal, second terminal, and third terminal is coupled to respectively a first lead, a second lead, and a third lead of said semiconductor package.
19. The semiconductor package of claim 11 , wherein said semiconductor package is a leadless package.
20. The semiconductor package of claim 11 , wherein said III-nitride transistor comprises a depletion-mode GaN.