VSWR compensation circuits for RF transmit chain
View Patent ↗The present invention provides a method and apparatus for compensating the output of a transmitter stage ( 50 ) of a communications system. A communications apparatus has a transmitter stage ( 50 ) providing a variable control voltage which varies the power of the transmitter stage. The impedance at the output of the transmitter stage. ( 50 ) varies as the power varies. A control generation circuit compares a reference voltage to the variable control voltage to produce a control signal (VvswrC). A compensated load ( 40 ) coupled to the output of the transmitter stage ( 50 ) has active component (s) whose' impedance varies in response to the control signal (VvsweC) so as to compensate for the impedance at the output of the transmitter stage ( 50 ).
1. A communications apparatus having a transmitter stage providing a variable control voltage which varies a power of the transmitter stage, an impedance at an output of the transmitter stage varying as the power varies, comprising:
a control generation circuit comparing a reference voltage to the variable control voltage to produce a control signal; and
a compensated load coupled to the output of the transmitter stage having at least one active component whose impedance varies in response to the control signal so as to compensate for the impedance at the output of the transmitter stage.
2. The apparatus of claim 1 , wherein the at least one active component comprises a field effect transistor (FET) having a gate, a source, and a drain, and the at least one active component further comprises:
a bias circuit converting the control signal to a bias voltage;
a resistor Rf coupling the output impedance of the transmitter to the drain of the FET; and
a resistor Rp connecting the source of the FET to the drain of the FET to keep the transistor's drain to source voltage near zero; wherein
the gate of the FET receives the bias voltage so as to vary the impedance of the compensated load as a function of the bias voltage.
3. The apparatus of claim 2 , wherein the impedance of the compensated load is varied by choosing the value of Rf.
4. The apparatus of claim 2 wherein the impedance of the compensated load is proportional to Rf+Ron and inversely proportional to the bias voltage.
5. The apparatus of claim 2 , wherein the impedance of the compensated load is varied by choosing the value of the reference voltage.
6. The apparatus of claim 2 , further comprising a DC shift circuit having a shift current Iref input to the gate of the FET transistor and an identical current Iref input to the drain and the source of the FET through a first resistor and a second resistor so as to shift the voltage of the gate of the FET.
7. The apparatus of claim 1 wherein the at least one active component further comprises:
a bias circuit configured to convert the control signal into a bias current;
a BJT Transistor T 1 ; and
a BJT Transistor T 2 ,
wherein transistor T 1 and T 2 are coupled through their bases so as to form a passive impedance; and
wherein the bias current is input to the collector of the transistor T 2 so that the bias current adjusts the impedance of the active component(s).
8. The apparatus of claim 7 , wherein as the bias current varies from 0 to 250uA, the impedance of compensated load varies from a high impedance to 100 ohms.
9. The apparatus of claim 1 , wherein the control voltage controls a variable gain amplifier.
10. A method for compensating an output impedance of a transmitter stage, the transmitter stage providing a variable control voltage which varies a power of the transmitter stage, the impedance at the output of the transmitter stage varying as the power varies, comprising the steps of:
generating a control signal by comparing a reference voltage to the variable control voltage to produce a control signal; and
compensating for the impedance at the output of the transmitter stage with a compensated load coupled to the output of the transmitter stage having at least one active component whose impedance varies in response to the control signal.
11. The method of claim 10 , wherein the at least one active component comprises a field effect transistor (FET) having a gate, a source, and a drain, and the at least one active component further comprises a resistor Rf coupling the output impedance of the transmitter to the drain of the FET, a resistor Rp connecting the drain of the FET to the source of the FET to keep the transistor's drain to source voltage near zero, and the gate of the FET receives the control signal, comprising the steps of:
converting by a bias circuit the control signal to a bias voltage; and
adjusting the bias voltage so as to vary the impedance of the compensated load wherein the impedance of the compensated load is proportional to Rf+Ron and inversely proportional to the bias voltage.
12. The method of claim 11 , further comprising providing a DC shift circuit having a shift current Iref input to the gate of the FET transistor and an identical current Iref input to the drain and the source of the FET through a first resistor and a second resistor, and shifting the voltage of the gate of the FET so that adjusting the bias voltage varies the impedance at the compensated load without the transistor becoming active at high voltages.
13. The method of claim 10 wherein the at least one active component further comprises:
a bias circuit configured to convert the control signal into a bias current; a BJT Transistor T 1 ; and a BJT Transistor T 2 , wherein transistor T 1 and T 2 are coupled through their bases so as to form a passive impedance; and wherein the bias current is input to the collector of the transistor T 2 so that the bias current adjusts the impedance of the active component(s), further comprising the step of:
adjusting the bias current so as to vary the load compensation as a function of the bias current.