Phase-locked loop
View Patent ↗A PLL circuit ( 1 a, 1 b ) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump ( 20 ) is arranged to generate an output signal based on the up and down signals and a loop filter ( 30 ) is arranged to generate a frequency-control signal based on the output signal of the charge pump ( 20 ). Furthermore, a VCO ( 40 a , 40 b ) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO ( 40 a , 40 b ) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz. A programmable first frequency divider ( 50 ) is arranged to generate the pixel-clock signal by frequency division of the oscillating signal, and a programmable second frequency divider ( 60 ) is arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.
1. A phase-locked loop circuit for generating a pixel-clock signal based on a horizontal synchronization signal, comprising:
a phase-frequency detector having an input to receive the horizontal synchronization signal and a frequency divided pixel-clock signal, and arranged to generate up and down signals based on the horizontal synchronization signal and the frequency-divided pixel-clock signal;
a charge pump having an input to receive the up and down signals from the phase-frequency detector, and arranged to generate an output signal based on the up and down signals;
a loop filter having an input to receive the output signal from the charge pump, and arranged to generate a frequency-control signal based on the output signal of the charge pump;
a voltage-controlled oscillator having an input to receive the frequency-control signal from the loop filter, and arranged to generate an oscillating signal and adjust a frequency of the oscillating signal in response to the frequency-control signal, wherein the voltage-controlled oscillator is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz;
a programmable first frequency divider having an input to receive the oscillating signal from the voltage-controlled oscillator, and arranged to generate the pixel-clock signal by frequency division of the oscillating signal; and
a programmable second frequency divider having an input to receive the pixel-clock signal from the programmable first frequency divider, and arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.
2. The phase-locked loop circuit according to claim 1 , wherein the voltage-controlled oscillator is an LC-tank voltage-controlled oscillator.
3. The phase-locked loop circuit according to claim 2 , wherein the voltage-controlled oscillator comprises a first capacitor, an inductor, and a varactor diode, wherein the varactor diode is responsive to the frequency-control signal for adjusting the frequency of the oscillating signal.
4. The phase-locked loop circuit according to claim 3 , wherein the voltage-controlled oscillator comprises one or more switchable capacitors arranged to be selectively connected in parallel with the first capacitor based on a calibration signal for calibrating the tuning range of the voltage-controlled oscillator.
5. The phase-locked loop circuit according to claim 4 , further comprising a calibration unit adapted to detect, based on the frequency-control signal, whether a target frequency of the oscillating signal is outside the tuning range of the voltage-controlled oscillator and, in response to the target frequency of the oscillating signal being outside the tuning range of the voltage-controlled oscillator, to generate the calibration signal for calibrating the tuning range of the voltage-controlled oscillator.
6. The phase-locked loop circuit according claim 5 , wherein the tuning range of the voltage-controlled oscillator comprises the frequency 5 GHz.
7. The phase-locked loop circuit according to claim 6 , wherein the programmable first frequency divider is adapted to be programmed to perform frequency division with even frequency divisors between and including 16 and 370.
8. The phase-locked loop circuit according to claim 7 , wherein the phase-locked loop circuit is included in a video front-end sampling circuit.
9. The phase-locked loop circuit according to claim 7 , wherein the phase-locked loop circuit is included in an integrated circuit.
10. The phase-locked loop circuit according to claim 7 , wherein the phase-locked loop circuit is included in electronic apparatus.
11. The phase-locked loop circuit according to claim 10 , wherein the electronic apparatus is a television set, a liquid-crystal display, a computer monitor, or a projector.
12. The phase-locked loop circuit according to claim 1 , wherein the voltage-controlled oscillator comprises a first capacitor, an inductor, and a varactor diode, wherein the varactor diode is responsive to the frequency-control signal for adjusting the frequency of the oscillating signal.
13. The phase-locked loop circuit according to claim 12 , wherein the voltage-controlled oscillator comprises one or more switchable capacitors arranged to be selectively connected in parallel with the first capacitor based on a calibration signal for calibrating the tuning range of the voltage-controlled oscillator.
14. The phase-locked loop circuit according to claim 13 , further comprising a calibration unit adapted to detect, based on the frequency-control signal, whether a target frequency of the oscillating signal is outside the tuning range of the voltage-controlled oscillator and, in response to the target frequency of the oscillating signal being outside the tuning range of the voltage-controlled oscillator, to generate the calibration signal for calibrating the tuning range of the voltage-controlled oscillator.
15. The phase-locked loop circuit according to claim 14 , wherein the tuning range of the voltage-controlled oscillator comprises the frequency 5 GHZ.
16. The phase-locked loop circuit according to claim 15 , wherein the programmable first frequency divider is adapted to be programmed to perform frequency division with even frequency divisors between and including 16 and 370.
17. The phase-locked loop circuit according to claim 1 , further comprising a calibration unit adapted to detect, based on the frequency-control signal, whether a target frequency of the oscillating signal is outside the tuning range of the voltage-controlled oscillator and, in response to the target frequency of the oscillating signal being outside the tuning range of the voltage-controlled oscillator, to generate the calibration signal for calibrating the tuning range of the voltage-controlled oscillator.
18. The phase-locked loop circuit according to claim 17 , wherein the tuning range of the voltage-controlled oscillator comprises the frequency 5 GHZ.
19. The phase-locked loop circuit according to claim 17 , wherein the programmable first frequency divider is adapted to be programmed to perform frequency division with even frequency divisors between and including 16 and 370.
20. The phase-locked loop circuit according to claim 19 , wherein the phase-locked loop circuit is included in a video front-end sampling circuit of a television set, a liquid-crystal display, a computer monitor, or a projector.