Granted Patent B2

US 8,289,309 · App. 13/064,129 · Granted Oct 16, 2012

Abstract

Claims (60)

1. An inverter circuit comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor each having channels of same conduction type;

a first capacity element; and

an input terminal and an output terminal,

wherein the first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto,

the second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a voltage of a first terminal which is a source or a drain of the fourth transistor and a voltage of the output terminal or a potential difference corresponding thereto,

the third transistor makes or breaks electrical connection between the first terminal and a third voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the third voltage line or a potential difference corresponding thereto,

the fourth transistor makes or breaks electrical connection between the first capacity element and a gate of the second transistor in response to a first control signal applied to a gate of the fourth transistor,

the fifth transistor makes or breaks electrical connection between the first capacity element and a fourth voltage line in response to a second control signal applied to a gate of the fifth transistor, and

the first capacity element is inserted between a source or a drain not connected to the fourth voltage line of the fifth transistor and a fifth voltage line.

2. An inverter circuit comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor each having channels of same conduction type;

a first capacity element; and

an input terminal and an output terminal,

wherein a gate of the first transistor is electrically connected to the input terminal, and one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal,

one terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal,

a gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the second transistor,

a gate of the fourth transistor is supplied with a first control signal, and one terminal of a drain and a source of the fourth transistor is electrically connected to the gate of the second transistor,

a gate of the fifth transistor is supplied with a second control signal, one terminal of a drain and a source of the fifth transistor is electrically connected to a fourth voltage line, and the other terminal of the fifth transistor is electrically connected to the other terminal of the fourth transistor, and

the first capacity element is inserted between the other terminal of the fifth transistor and a fifth voltage line.

3. The inverter circuit according to claim 2 , further comprising:

a second capacity element inserted between the gate and the source of the second transistor.

4. The inverter circuit according to claim 3 , wherein

the capacity of the second capacity element is smaller than that of the first capacity element.

5. The inverter circuit according to claim 4 , wherein

the capacities of the first capacity element and the second capacity element satisfy the following expression:

C 1 ( V dd2 −V ss )/( C 1 +C 2 )> V th2

where C 1 is the capacity of the first capacity element, C 2 is the capacity of the second capacity element, V dd2 is a voltage of the fourth voltage line, V ss is a voltage of the first voltage line, and V th2 is a threshold voltage of the second transistor.

6. The inverter circuit according to claim 2 , wherein

the first voltage line, the third voltage line and the fifth voltage line have the same potential.

7. The inverter circuit according to claim 6 , wherein

the second voltage line and the fourth voltage line are connected to a power supply outputting a voltage higher than a common voltage of the first voltage line, the third voltage line and the fifth voltage line.

8. The inverter circuit according to claim 7 , wherein

the fourth voltage line is connected to a power supply outputting a voltage higher than the voltage of the second voltage line by a threshold voltage of the second transistor or over.

9. The inverter circuit according to claim 2 , wherein

the fourth transistor and the fifth transistor are alternately turned on and off so as not to be turned on simultaneously.

10. The inverter circuit according to claim 9 , wherein

the fourth transistor is turned on before a voltage of the input terminal falls.

11. The inverter circuit according to claim 9 , wherein

the fourth transistor is turned on after a voltage of the input terminal falls.

12. A display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form, the drive section including a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, each of the inverter circuits comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor each having channels of same conduction type;

a first capacity element; and

an input terminal and an output terminal,

wherein the first transistor makes or breaks electrical connection between the output terminal and a first voltage line in response to a potential difference between a voltage of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto,

the second transistor makes or breaks electrical connection between a second voltage line and the output terminal in response to a potential difference between a voltage of a first terminal which is a source or a drain of the fourth transistor and a voltage of the output terminal or a potential difference corresponding thereto,

the third transistor makes or breaks electrical connection between the first terminal and a third voltage line in response to a potential difference between the voltage of the input terminal and a voltage of the third voltage line or a potential difference corresponding thereto,

the fourth transistor makes or breaks electrical connection between the first capacity element and a gate of the second transistor in response to a first control signal applied to a gate of the fourth transistor,

the fifth transistor makes or breaks electrical connection between the first capacity element and a fourth voltage line in response to a second control signal applied to a gate of the fifth transistor, and

the first capacity element is inserted between a source or a drain not connected to the fourth voltage line of the fifth transistor and a fifth voltage line.

13. A display with a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of pixels arranged in a matrix form, the drive section including a plurality of inverter circuits each arranged corresponding to the scanning lines to drive each of the pixels, each of the inverter circuits comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor each having channels of same conduction type;

a first capacity element; and

an input terminal and an output terminal,

wherein a gate of the first transistor is electrically connected to the input terminal, and one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal,

one terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal,

a gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the second transistor,

a gate of the fourth transistor is supplied with a first control signal, and one terminal of a drain and a source of the fourth transistor is electrically connected to the gate of the second transistor,

a gate of the fifth transistor is supplied with a second control signal, one terminal of a drain and a source of the fifth transistor is electrically connected to a fourth voltage line, and the other terminal of the fifth transistor is electrically connected to the other terminal of the fourth transistor, and

the first capacity element is inserted between the other terminal of the fifth transistor and a fifth voltage line.

Assignments (6)