Non-volatile memory device
View Patent ↗A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.
1. A method for fabricating a non-volatile memory device comprises:
forming a gate electrode on a semiconductor layer;
forming a thermal oxidation layer and a NSG layer on a surface of the gate electrode;
removing the NSG layer located only in a memory cell region by a HF treatment to form a notch or wedge shape gap extending into a bottom end of the gate electrode;
forming a charge storage layer on a surface of the gate electrode and into the notch or wedge shape gap; and
selectively removing the charge storage layer to remain only inside the notch or wedge shape gap of the memory cell region.
2. A method according to claim 1 , wherein
said charge storage layer is formed to store one bit information at each side of said gate electrode.
3. A method according to claim 1 , wherein
said memory cell region comprises a pair of silicon oxide layers,
said charge storage layer is of a silicon nitride layer, which is formed between said pair of silicon oxide layers to form a ONO layered structure.
4. A method according to claim 3 , wherein
said memory cell region comprises a LDD layer located under said ONO layered structure; and a side wall insulating layer formed on a side surface of said gate electrode,
said side wall insulating layer is located above said ONO layered structure.
5. A method according to claim 1 , wherein
said charge storage layer is of a poly-silicon layer.
6. A method according to claim 4 , wherein
said side wall insulating layer is of a silicon nitride layer.
7. A method according to claim 4 , wherein
said side wall insulating layer is formed using said silicon oxide layer arranged above the storage charge layer of the ONO layered structure.