Delay circuit, semiconductor control circuit, display device and electronic device
View Patent ↗Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.
1. A semiconductor control circuit for supplying a control signal to a circuit to be controlled, said semiconductor control circuit comprising:
a delay circuit for receiving a detection pulse, and outputting a plurality of delayed signals having different amounts of delay according to transistor characteristics;
a sampling circuit for sampling the delayed signals of said delay circuit with said detection pulse as a reference signal; and
a hysteresis characteristic generating circuit for generating the control signal having a hysteresis characteristic according to a difference between the plurality of delayed signals sampled by said sampling circuit.
2. The semiconductor control circuit according to claim 1 , wherein
said delay circuit includes a plurality of delay series of different channel types.
3. The semiconductor control circuit according to claim 1 , wherein
said delay circuit is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal,
said delay circuit including
an output section configured to output a delayed signal,
two power supplies, and
a delay inverter,
said delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, said first transistor and said second transistor being connected in series with each other between said output section and one power supply, and said delay inverter has a third transistor of a different channel type from said first transistor and said second transistor for one of a second charge and a second discharge, said third transistor being connected in parallel with one of said first transistor and said second transistor.
4. The semiconductor control circuit according to claim 3 , wherein
a pulse of opposite phase in front of an input of said delay inverter is supplied to gates of said first transistor and said second transistor, and one of the first charge and the first discharge is performed with the pulse of opposite phase in front of the input of said delay inverter, and
an input pulse of said delay inverter is supplied to a gate of said third transistor, and one of the second charge and the second discharge is performed with the input pulse of said delay inverter.
5. A display device comprising:
an effective display section;
at least one peripheral circuit for performing processing related to operation of said effective display section; and
a semiconductor control circuit for outputting a control signal with said peripheral circuit as a circuit to be controlled; wherein
said effective display section, said peripheral circuit, and said semiconductor control circuit being formed integrally with each other on an insulating substrate,
said semiconductor control circuit includes
a delay circuit for receiving a detection pulse, and outputting a plurality of delayed signals having different amounts of delay according to transistor characteristics,
a sampling circuit for sampling the delayed signals of said delay circuit with said detection pulse as a reference signal, and
a hysteresis characteristic generating circuit for generating the control signal having a hysteresis characteristic according to a difference between the plurality of delayed signals sampled by said sampling circuit.
6. An electronic device having a display device, wherein
said display device includes
an effective display section;
at least one peripheral circuit for performing processing related to operation of said effective display section; and
a semiconductor control circuit for outputting a control signal with said peripheral circuit as a circuit to be controlled;
said effective display section, said peripheral circuit, and said semiconductor control circuit being formed integrally with each other on an insulating substrate, and
said semiconductor control circuit includes
a delay circuit for receiving a detection pulse, and outputting a plurality of delayed signals having different amounts of delay according to transistor characteristics,
a sampling circuit for sampling the delayed signals of said delay circuit with said detection pulse as a reference signal, and
a hysteresis characteristic generating circuit for generating the control signal having a hysteresis characteristic according to a difference between the plurality of delayed signals sampled by said sampling circuit.