Organic light emitting display and method of fabricating the same

1. An organic light emitting display, comprising:

a substrate, the substrate including a first thin film transistor region and a second thin film transistor region;

a buffer layer on the substrate;

a first semiconductor layer and a second semiconductor layer on the buffer layer;

a gate insulating layer on the substrate;

gate electrodes on the gate insulating layer, the gate electrodes corresponding to the first semiconductor layer and the second semiconductor layer, respectively;

source/drain electrodes insulated from the gate electrode, one of the source/drain electrodes being electrically connected to the first semiconductor layer and another of the source drain electrodes being electrically connected to the second semiconductor layer, respectively;

an insulating layer on the substrate;

a first electrode connected to the one source/drain electrode electrically connected to the first semiconductor layer;

an organic layer on the first electrode; and

a second electrode on the organic layer,

wherein portions of the buffer layer corresponding to a source/drain region of the first semiconductor layer include a metal catalyst, and

wherein the portions of the buffer layer including the metal catalyst have a thickness greater than other portions of the buffer layer.

2. The organic light emitting display as claimed in claim 1 , wherein the first semiconductor layer is a driving semiconductor layer.

3. The organic light emitting display as claimed in claim 1 , wherein the first semiconductor layer includes a polycrystalline silicon layer crystallized by a metal catalyst.

4. The organic light emitting display as claimed in claim 1 , wherein the second semiconductor layer includes a polycrystalline silicon layer crystallized by a solid phase crystallization method.

5. The organic light emitting display as claimed in claim 1 , wherein the metal catalyst includes at least one of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, and Cd.

6. The organic light emitting display as claimed in claim 1 , further comprising any one of a silicon oxide layer, a silicon nitride layer, or a double layer thereof between the buffer layer and first semiconductor layer and between the buffer layer and the second semiconductor layer.

7. The organic light emitting display as claimed in claim 1 , wherein the buffer layer has a thickness of about 400 Å to about 9,900 Å.

8. The organic light emitting display as claimed in claim 1 , wherein the source/drain electrodes electrically connected to the first semiconductor layer contact the first semiconductor layer at the source/drain region of the first semiconductor layer that overlies the portions of buffer layer including the metal catalyst.

9. A method for fabricating an organic light emitting display, the method comprising:

providing a substrate including a first thin film transistor region and a second thin film transistor region;

forming a buffer layer on the substrate;

forming a first semiconductor layer and a second semiconductor layer on the buffer layer;

forming an etch stop layer on the first semiconductor layer and the second semiconductor layer;

forming source/drain electrodes such that the source/drain electrodes are electrically connected to the first semiconductor layer and the second semiconductor layer, respectively;

forming a gate insulating layer on the substrate;

forming gate electrodes on the gate insulating layer such that one gate electrode corresponds to the first semiconductor layer and another gate electrode corresponds to the second semiconductor layer;

forming an insulating layer on the substrate;

forming a first electrode such that the first electrode is connected to the one source/drain electrode corresponding to the first semiconductor layer;

forming an organic layer on the first electrode such that the organic layer includes an organic light emitting layer; and

forming a second electrode on the organic layer,

wherein portions of the buffer layer on a lower portion of the first semiconductor layer include a metal catalyst, and

wherein the portions of the buffer layer including the metal catalyst have a thickness greater than other portions of the buffer layer.

10. The method as claimed in claim 9 , further comprising:

forming a metal catalytic layer on the buffer layer,

diffusing the metal catalyst of the metal catalytic layer to the buffer layer by heat treating the substrate, and

removing the metal catalytic layer.

11. The method as claimed in claim 10 , wherein the portions of the buffer layer including the metal catalyst are a metal catalytic region and correspond to the first semiconductor layer.

12. The method as claimed in claim 11 , further comprising etching a surface of the buffer layer except for the metal catalytic region after diffusing the metal catalyst to the buffer layer.

13. The method as claimed in claim 12 , wherein about 100 Å to about 2,000 Å of the buffer layer is etched.

14. The method as claimed in claim 9 , wherein forming the first semiconductor layer includes:

crystallizing a polycrystalline silicon layer with the metal catalyst, and

patterning the crystallized polycrystalline silicon layer.

15. The method as claimed in claim 9 , wherein forming the second semiconductor layer includes:

crystallizing a polycrystalline silicon layer by a solid phase crystallization method, and

patterning the crystallized polycrystalline silicon layer.

16. An organic light emitting display, comprising:

a substrate, the substrate including a first thin film transistor region and a second thin film transistor region;

a buffer layer on the substrate;

a first semiconductor layer and a second semiconductor layer on the buffer layer;

an etch stop layer on the first semiconductor layer and the second semiconductor layer;

source/drain electrodes, one of the source/drain electrodes being electrically connected to the first semiconductor layer and another of the source/drain electrodes being electrically connected to the second semiconductor layer;

a gate insulating layer on the substrate;

gate electrodes on the gate insulating layer, the gate electrodes corresponding to the first semiconductor layer and the second semiconductor layer, respectively;

an insulating layer on the substrate;

a first electrode connected to the one source/drain electrode electrically connected to the first semiconductor layer;

an organic layer on the first electrode; and

a second electrode on the organic layer,

wherein portions of the buffer layer corresponding to a source/drain region of the first semiconductor layer include a metal catalyst, and

wherein the portions of the buffer layer including the metal catalyst have a thickness greater than other portions of the buffer layer.

17. The organic light emitting display as claimed in claim 16 , wherein the first semiconductor layer is a driving semiconductor layer.

18. The organic light emitting display as claimed in claim 16 , wherein the first semiconductor layer includes a polycrystalline silicon layer crystallized by a metal catalyst.

19. The organic light emitting display as claimed in claim 16 , wherein the second semiconductor layer includes a polycrystalline silicon layer crystallized by a solid phase crystallization method.

20. The organic light emitting display as claimed in claim 16 , further comprising any one of a silicon oxide layer, a silicon nitride layer, or a double layer thereof between the first semiconductor layer and the buffer layer and between the second semiconductor layer and the buffer layer.

21. The organic light emitting display as claimed in claim 16 , wherein the buffer layer has a thickness of about 400 Å to about 9,900 Å.

22. An organic light emitting display, comprising:

a substrate, the substrate including a first thin film transistor region and a second thin film transistor region;

gate electrodes on the first thin film transistor region and the second thin film transistor region of the substrate, respectively;

a gate insulating layer on the substrate;

a first semiconductor layer and a second semiconductor layer on the gate insulating layer;

an etch stop layer on the first semiconductor layer and the second semiconductor layer;

source/drain electrodes, one of the source/drain electrodes being electrically connected to the first semiconductor layer and another of the source drain electrodes being electrically connected to the second semiconductor layer;

an insulating layer on the substrate;

a first electrode connected to the one source/drain electrode electrically connected to the first semiconductor layer;

an organic layer on the first electrode; and

a second electrode on the organic layer,

wherein portions of the gate insulating layer corresponding to a source/drain region of the first semiconductor layer include a metal catalyst, and

wherein the portions of the gate insulating layer including the metal catalyst have a thickness greater than other portion of the gate insulating layer.

23. The organic light emitting display as claimed in claim 22 , wherein the first semiconductor layer is a driving semiconductor layer.

24. The organic light emitting display as claimed in claim 22 , wherein the first semiconductor layer includes a polycrystalline silicon layer crystallized by a metal catalyst.

25. The organic light emitting display as claimed in claim 22 , wherein the second semiconductor layer includes a polycrystalline silicon layer crystallized by a solid phase crystallization method.

26. The organic light emitting display as claimed in claim 22 , wherein the first semiconductor layer includes a metal catalyst.

27. The organic light emitting display as claimed in claim 22 , further comprising any one of a silicon oxide layer, a silicon nitride layer, or a double layer thereof between the first semiconductor layer and the buffer layer and between the second semiconductor layer and the buffer layer.

28. The organic light emitting display as claimed in claim 22 , wherein the buffer layer has a thickness of about 400 Å to about 9,900 Å.

29. A method for fabricating an organic light emitting display, the method comprising:

providing a substrate that includes a first thin film transistor region and a second thin film transistor region;

forming gate electrodes on the first thin film transistor region and the second thin film transistor region of the substrate, respectively;

forming a gate insulating layer on the substrate;

forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer;

forming an etch stop layer on the first semiconductor layer and the second semiconductor layer;

forming source/drain electrodes such that one of the source/drain electrodes is electrically connected to the first semiconductor layer and another of the source/drain electrodes is electrically connected to the second semiconductor layer;

forming an insulating layer on the substrate;

forming a first electrode connected to the one source/drain electrode electrically connected to the first semiconductor layer;

forming an organic layer on the first electrode such that the organic layer includes an organic light emitting layer; and

forming a second electrode on the organic layer,

wherein at least a portion of the gate insulating layer on a lower region of the first semiconductor layer is a metal catalytic region and include a metal catalyst, and

wherein the portions of the gate insulating layer including the metal catalyst have a thickness greater than other portion of the gate insulating layer.

30. The method as claimed in claim 29 , further comprising:

forming a metal catalytic layer on the gate insulating layer,

diffusing a metal catalyst of the metal catalytic layer to the gate insulating layer by heat treating the substrate, and

removing the metal catalytic layer.

31. The method as claimed in claim 29 , wherein the metal catalytic region includes the metal catalyst of the gate insulating layer, the metal catalytic region corresponding to the first semiconductor layer.

32. The method as claimed in claim 31 , further comprising etching a surface of the gate insulating layer except for the metal catalytic region after diffusing the metal catalyst to the gate insulating layer.

33. The method as claimed in claim 29 , wherein forming the first semiconductor layer includes:

crystallizing a polycrystalline silicon layer with the metal catalyst, and

patterning the crystallized polycrystalline silicon layer.

34. The method as claimed in claim 29 , wherein forming the second semiconductor layer includes:

crystallizing a polycrystalline silicon layer by a solid phase crystallization method, and

patterning the crystallized polycrystalline silicon layer.