Semiconductor device having depletion type MOS transistor
View Patent ↗A depletion type MOS transistor includes a well region having a first conductivity type and formed on a semiconductor substrate, a gate insulating film formed on the well region, and a gate electrode formed on the gate insulating film. Source and drain regions having a second conductivity type different from the first conductivity type are formed on respective sides of the gate electrode and within the well region. A first low concentration impurity region has the second conductivity type and is formed below the gate insulating film between the source and drain regions and within the well region. A second low concentration impurity region has the first conductivity type and is formed below the first low concentration impurity region between the source and drain regions and within the well region.
1. A depletion normally-on type MOS transistor, comprising:
a well region having a first conductivity type formed on a semiconductor substrate;
a gate insulating film formed on the well region;
a gate electrode formed on the gate insulating film, the gate electrode having a second conductivity type different from the first conductivity type;
source and drain regions formed on respective sides of the gate electrode and within the well region, the source and drain regions having the second conductivity type;
a first low concentration impurity region having the second conductivity type and being formed below the gate insulating film between the source and drain regions and within the well region, the first low concentration impurity region and the gate electrode having the same conductivity type to achieve normally-on operation of the MOS transistor; and
a second low concentration impurity region having the first conductivity type and being formed within the well region and below the first low concentration impurity region between the source and drain regions, the second low concentration impurity region having a maximum peak concentration not greater than that of the first low concentration impurity region and greater than that of the well region.
2. A depletion normally-on type MOS transistor according to claim 1 ; wherein the second low concentration impurity region is disposed apart from the source and drain regions.
3. A depletion normally-on type MOS transistor according to claim 2 ; wherein the second low concentration impurity region is set at a distance of 0.5 μm to 1.5 μm from the source and drain regions.
4. A depletion normally-on type MOS transistor according to claim 1 ; wherein the second low concentration impurity region has a peak concentration of 5.0×10 16 /cm 3 to 1.0×10 18 /cm 3 .
5. A depletion normally-on type MOS transistor according to claim 4 ; wherein the first low concentration impurity region has a peak concentration of 1.0×10 17 /cm 3 to 5.0×10 18 /cm 3 .
6. A depletion normally-on type MOS transistor according to claim 1 ; wherein the second low concentration impurity region is disposed in direct contact with each of the source and drain regions.
7. A depletion normally-on type MOS transistor according to claim 1 ; wherein the second low concentration impurity region is not disposed in direct contact with each of the source and drain regions.
8. A depletion normally-on type MOS transistor according to claim 1 ; wherein the first conductivity type is a P-type conductivity and the second conductivity is an N-type conductivity.
9. A depletion normally-on type MOS transistor according to claim 1 ; wherein the second low concentration impurity region has an impurity concentration higher than that of the well region.
10. A semiconductor device comprising a depletion normally-on type MOS transistor according to claim 1 .
11. A semiconductor device according to claim 10 ; wherein the second low concentration impurity region is disposed apart from the source and drain regions.
12. A semiconductor device according to claim 11 ; wherein the second low concentration impurity region is set at a distance of 0.5 μm to 1.5 μm from the source and drain regions.
13. A semiconductor device according to claim 10 ; wherein the second low concentration first conductivity type impurity region has a peak concentration of 5.0×10 18 /cm 3 to 1.0×10 18 /cm 3 .
14. A semiconductor device according to claim 13 ; wherein the first low concentration impurity region has a peak concentration of 1.0×10 17 /cm 8 to 5.0×10 18 /cm 3 .
15. A semiconductor device according to claim 10 ; wherein the second low concentration impurity region is disposed in direct contact with each of the source and drain regions.
16. A semiconductor device according to claim 10 ; wherein the second low concentration impurity region is not disposed in direct contact with each of the source and drain regions.
17. A semiconductor device according to claim 10 ; wherein the second low concentration impurity region is disposed in direct contact with the first low concentration impurity region.
18. A semiconductor device according to claim 10 ; wherein the second low concentration impurity region has an impurity concentration higher than that of the well region.
19. A semiconductor device according to claim 10 ; wherein the depletion normally-on type MOS transistor comprises a depletion normally-on type N-channel MOS transistor.
20. A semiconductor device according to claim 19 ; wherein the first conductivity type is a P-type conductivity and the second conductivity type is N-type conductivity.