Fully differential adaptive bandwidth PLL with differential supply regulation
View Patent ↗Provided is a fully differential adaptive bandwidth phase locked loop with differential supply regulation. One fully differential phase locked loop includes a differential active loop filter and regulator coupled to an output of a differential charge pump, a differential voltage-controlled oscillator coupled to differential control voltages developed by the differential active loop filter and regulator, and a bias circuit coupled to the differential control voltages and providing a bias current to the differential charge pump.
1. A fully differential adaptive bandwidth phase locked loop (PLL) with differential supply regulation, the PLL comprising:
a differential active loop filter and regulator (DALFR) coupled to an output of a differential charge pump;
a differential voltage-controlled oscillator (DVCO) coupled to differential control voltages developed by the DALFR; and
a bias circuit coupled to the differential control voltages and providing a bias current to the differential charge pump;
wherein the DALFR includes:
an active loop filter amplifier/regulator (ALFA/R);
first and second feedback networks for respective first and second differential outputs of the ALFA/R;
the first feedback network including a MOS capacitor and a PMOS transistor that is configured as a MOS resistor;
the PMOS transistor having a gate coupled to the second differential output of the ALFA/R.
2. The PLL of claim 1 , wherein the bias current is derived from the differential control voltages.
3. The PLL of claim 1 , wherein the differential charge pump comprises a fully differential all NMOS charge pump.
4. The PLL of claim 1 , wherein the DALFR comprises:
a plurality of capacitors and resistors configured to form first and second feedback networks for respective first and second differential outputs of the ALFA/R.
5. The PLL of claim 1 , wherein the DALFR comprises:
the second feedback network including a MOS capacitor and an NMOS transistor that is configured as a MOS resistor;
the NMOS transistor having a gate coupled to the first differential output of the ALFA/R.
6. The PLL of claim 1 , wherein the bias circuit comprises:
a first transistor coupled to the differential control voltages;
a second transistor in series with the first transistor and coupled to a third transistor;
the third transistor being configured to provide the bias current to the differential charge pump.
7. The PLL of claim 1 , wherein the bias circuit comprises:
a first transistor coupled to the differential control voltages;
second and third transistors forming a gate tied pair of PMOS transistors;
the second transistor in series with the first transistor;
the third transistor being configured to provide the bias current to the differential charge pump.
8. The PLL of claim 1 , wherein the DVCO comprises a differential inverter-ring voltage controlled oscillator.
9. The PLL of claim 1 , wherein the DVCO comprises a differential output buffer.
10. The PLL of claim 1 , further comprising a differential frequency divider coupled to the DVCO.
11. The PLL of claim 1 , further comprising a differential phase frequency detector coupled to the differential charge pump.
12. The PLL of claim 1 , wherein the DALFR is configured to develop differential control voltages ranging substantially up to a transistor saturation voltage below a supply voltage for the PLL, thereby increasing an operating frequency range of the PLL.
13. The PLL of claim 1 , wherein the DALFR, the DVCO and the bias circuit are configured so that a ratio of loop bandwidth to operating frequency for the PLL is substantially constant over an operating frequency range of the PLL.
14. The PLL of claim 1 , wherein the DALFR, the DVCO and the bias circuit are configured so that a damping factor for the PLL is substantially constant over an operating frequency range of the PLL.
15. A fully differential adaptive bandwidth phase locked loop (PLL) with differential supply regulation, the PLL comprising:
a differential active loop filter and regulator (DALFR) coupled to an output of a differential charge pump;
a differential voltage-controlled oscillator (DVCO) coupled to differential control voltages developed by the DALFR; and
a bias circuit coupled to the differential control voltages and providing a bias current to the differential charge pump;
wherein the DALFR includes:
an active loop filter amplifier/regulator (ALFA/R);
first and second feedback networks for respective first and second differential outputs of the ALFA/R;
the second feedback network including a MOS capacitor and an NMOS transistor that is configured as a MOS resistor;
the NMOS transistor having a gate coupled to the first differential output of the ALFA/R.
16. The PLL of claim 15 , wherein the bias current is derived from the differential control voltages.
17. The PLL of claim 15 , wherein the differential charge pump comprises a fully differential all NMOS charge pump.
18. The PLL of claim 15 , wherein the DALFR comprises:
a plurality of capacitors and resistors configured to form first and second feedback networks for respective first and second differential outputs of the ALFA/R.
19. The PLL of claim 15 , wherein the bias circuit comprises:
a first transistor coupled to the differential control voltages;
a second transistor in series with the first transistor and coupled to a third transistor;
the third transistor being configured to provide the bias current to the differential charge pump.
20. A fully differential adaptive bandwidth phase locked loop (PLL) comprising:
a differential active loop filter and regulator (DALFR) including:
an active loop filter amplifier/regulator (ALFA/R);
first and second feedback networks for respective first and second differential outputs of the ALFA/R;
the first feedback network including a MOS capacitor and a PMOS transistor that is configured as a MOS resistor, and
the PMOS transistor having a gate coupled to the second differential output of the ALFA/R.