Semiconductor integrated circuit device with reduced leakage current
View Patent ↗The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
1. A semiconductor device comprising:
a plurality of static type memory cells each having a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor, a drain of the first P-channel MOS transistor, a drain of the first N-channel MOS transistor, a gate of the second P-channel MOS transistor and a gate of the second N-channel MOS transistor being connected to each other, and a drain of the second P-channel MOS transistor, a drain of the second N-channel MOS transistor, a gate of the first P-channel MOS transistor and a gate of the first N-channel MOS transistor being connected to each other;
a power line connected to sources of the first and second P-channel MOS transistors of the plurality of static type memory cells;
a source line connected to sources of the first and second N-channel MOS transistors of the plurality of static type memory cells; and
a power voltage control circuit that controls a power voltage of the plurality of static type memory cells which is defined as a potential difference between the power line and the source line, the power voltage control circuit having a third N-channel MOS transistor,
wherein, in a drain region of the first N-channel MOS transistor, a contact region thereof includes arsenic and an extension region thereof includes phosphorus,
wherein, in a drain region of the second N-channel MOS transistor, a contact region thereof includes arsenic and an extension region thereof includes phosphorus, and
wherein, in a drain region of the third N-channel MOS transistor, each of a contact region and an extension region thereof includes arsenic.
2. The semiconductor device according to claim 1 , further comprising:
an input/output circuit having a fourth N-channel MOS transistor,
wherein, in a drain region of the fourth N-channel MOS transistor, each of a contact region and an extension region thereof includes arsenic.
3. A semiconductor device comprising:
a plurality of static type memory cells each having a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor, a drain of the first P-channel MOS transistor, a drain of the first N-channel MOS transistor, a gate of the second P-channel MOS transistor and a gate of the second N-channel MOS transistor being connected to each other, and a drain of the second P-channel MOS transistor, a drain of the second N-channel MOS transistor, a gate of the first P-channel MOS transistor and a gate of the first N-channel MOS transistor being connected to each other;
a power line connected to sources of the first and second P-channel MOS transistors of the plurality of static type memory cells; and
a source line connected to sources of the first and second N-channel MOS transistors of the plurality of static type memory cells,
wherein, in a drain region of the first N-channel MOS transistor, a contact region thereof includes arsenic and an extension region thereof includes phosphorus,
wherein, in a drain region of the second N-channel MOS transistor, a contact region thereof includes arsenic and an extension region thereof includes phosphorus, and
wherein side wall layers are formed on side walls of each gate electrode of the first P-channel MOS transistor, the first N-channel MOS transistor, the second P-channel MOS transistor, and the second N-channel MOS transistor.
4. The semiconductor device according to claim 3 , further comprising:
a power voltage control circuit that controls a power voltage of the plurality of static type memory cells which is defined as a potential difference between the power line and the source line, the power voltage control circuit having a third N-channel MOS transistor.
5. The semiconductor device according to claim 4 ,
wherein, in a drain region of the third N-channel MOS transistor, each of a contact region and an extension region thereof includes arsenic.
6. The semiconductor device according to claim 5 ,
wherein side wall layers are formed on side walls of a gate electrode of the third N-channel MOS transistor.
7. The semiconductor device according to claim 3 , further comprising:
an input/output circuit having a fourth N-channel MOS transistor.
8. The semiconductor device according to claim 7 ,
wherein, in a drain region of the fourth N-channel MOS transistor, each of a contact region and an extension region thereof includes arsenic.
9. The semiconductor device according to claim 8 ,
wherein side wall layers are formed on side walls of a gate electrode of the fourth N-channel MOS transistor.
10. The semiconductor device according to claim 9 , further comprising:
a power voltage control circuit that controls a power voltage of the plurality of static type memory cells which is defined as a potential difference between the power line and the source line, the power voltage control circuit having a third N-channel MOS transistor.
11. The semiconductor device according to claim 10 ,
wherein, in a drain region of the third N-channel MOS transistor, each of a contact region and an extension region thereof includes arsenic.
12. The semiconductor device according to claim 11 ,
wherein side wall layers are formed on side walls of a gate electrode of the third N-channel MOS transistor.