Layout design method of semiconductor integrated circuit including regenerating a cell layout to set first and second distances and generating library data
View Patent ↗A layout design method of a semiconductor integrated circuit includes providing a cell layout including a cell that includes a gate or a plurality of gates extending in a first direction, a plurality of diffusion layers, a first boundary of the cell in parallel with the gate or the plurality of gates, a second boundary of the cell being in an opposite side of the first boundary of the cell, a first distance, a second distance, a third distance, and a fourth distance, regenerating the cell layout to set the first distance and the second distance to a first value, or to set the third distance and the fourth distance to a second value, and generating a library data of the cell for a placement and routing tool, based on the cell layout.
1. A layout design method of a semiconductor integrated circuit, said method comprising:
providing a cell layout including a cell that comprises:
a gate or a plurality of gates extending in a first direction;
a plurality of diffusion layers;
a first boundary of said cell in parallel with the gate or the plurality of gates;
a second boundary of said cell being in an opposite side of the first boundary of the cell;
a first distance between the first boundary and a closest diffusion layer of the plurality of diffusion layers from the first boundary;
a second distance between the second boundary and a closest diffusion layer of the plurality of diffusion layers from the second boundary;
a third distance between the first boundary and a closest gate of the gate or the plurality of gates from the first boundary; and
a fourth distance between the second boundary and a closest gate of the gate or the plurality of gates from the second boundary;
regenerating the cell layout to set the first distance and the second distance to a first value, or to set the third distance and the fourth distance to a second value, as executed by a processing unit of a computer; and
generating a library data of said cell for a placement and routing tool, based on said cell layout.
2. The layout design method according to claim 1 , further comprising:
recording the library data onto a storage device.
3. A non-transitory computer-readable storage medium enclosed with a computer program for the semiconductor integrated circuit according to claim 2 for executing the layout design method for semiconductor integrated circuits on a computer.
4. The layout design method according to claim 1 , further comprising: setting a layout of a semiconductor chip by arranging the cell in a second direction perpendicular to the first direction, using said library data.
5. The layout design method according to claim 1 , further comprising:
displaying the layout of said semiconductor chip on a display device.
6. The layout design method according to claim 1 , wherein the providing the cell layout comprises:
extracting a layout data of gate and/or diffusion layers corresponding to said gate or said plurality of gates and/or said plurality of diffusion layers from the cell layout; and
setting said first value and said second value in accordance with the extracted layout data.
7. The layout design method according to claim 1 , wherein said first distance and said second distance are equal, or said third distance and said fourth distance are equal.
8. The layout design method according to claim 1 , wherein said regenerating the cell layout comprises setting the first distance and the second distance to the first value, and setting the third distance and the fourth distance to a second value.
9. The layout design method according to claim 1 , wherein said first distance and said second distance are equal, and said third distance and said fourth distance are equal.