IP Library Granted Patent US 8,542,507
Granted Patent B2
US 8,542,507 · App. 13/069,534 · Granted Sep 24, 2013

Adaptive synchronous rectification control method and apparatus

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Quick Facts
Patent No.
US 8,542,507
App. No.
13/069,534
Granted
Sep 24, 2013
Kind
B2
Abstract

An adaptive synchronous rectification control circuit and a control method are developed. The control circuit comprises an adaptive circuit that generates a reference signal in response to a detection signal of a power converter. A clamped circuit clamps the reference signal at a threshold voltage if the reference signal equals or is greater than the threshold voltage. A switching circuit generates a control signal to control a synchronous switch of the power converter in response to the detection signal and the reference signal. The control method generates the reference signal in response to the detection signal. The reference signal is clamped at the threshold voltage if the reference signal equals or is greater than the threshold voltage. The method further generates the control signal to control the synchronous switch of the power converter in response to the detection signal and the reference signal.

Claims (34)

1. An adaptive synchronous rectification control circuit comprising:

an adaptive circuit generating a reference signal in response to a detection signal of a power converter;

a clamped circuit coupled to the adaptive circuit, in which the clamped circuit clamps the reference signal at a threshold voltage if the reference signal equals or is greater than the threshold voltage; and

a switching circuit generating a control signal to control a synchronous switch of the power converter in response to the detection signal and the reference signal.

2. The control circuit as claimed in claim 1 , wherein the adaptive circuit further comprises a sample-hold circuit for sampling and holding the detection signal for generating the reference signal.

3. The control circuit as claimed in claim 2 , wherein the adaptive circuit further comprises an amplifier coupled to the sample-hold circuit, the sample-hold circuit samples and holds the detection signal to generate a hold signal, the amplifier receives the hold signal to generate the reference signal in response to the hold signal and an amplifier coefficient.

4. The control circuit as claimed in claim 2 , wherein the adaptive circuit further comprises:

a rising edge detector generating a first sample signal in accordance with a rising edge of the detection signal; and

a falling edge detector generating a second sample signal in accordance with a falling edge of the detection signal;

wherein the first sample signal and the second sample signal are utilized to control the sample-hold circuit to sample and hold the detection signal for generating the reference signal.

5. The control circuit as claimed in claim 1 , wherein the clamped circuit comprises:

a transistor coupled between the adaptive circuit and a ground; and

an operational amplifier controlling the transistor in response to the reference signal and the threshold voltage;

wherein the transistor is turned on by the operational amplifier to clamp the reference signal at the threshold voltage if the reference signal equals or is greater than the threshold voltage.

6. The control circuit as claimed in claim 1 , wherein the switching circuit comprises;

a comparator comparing the detection signal with the reference signal to generating a switching signal; and

a PWM circuit generating the control signal in response to the switching signal.

7. The control circuit as claimed in claim 1 , wherein the detection signal is generated by present switching period of the power converter, and the reference signal is generated by sampling and holding the detection signal generated by previous switching period of the power converter.

8. The control circuit as claimed in claim 1 , wherein the detection signal is correlated to an input voltage of the power converter.

9. An adaptive synchronous rectification control method comprising:

generating a reference signal in response to a detection signal of a power converter;

clamping the reference signal at a threshold voltage if the reference signal equals or is greater than the threshold voltage; and

generating a control signal to control a synchronous switch of the power converter in response to the detection signal and the reference signal.

10. The method as claimed in claim 9 , further sampling and holding the detection signal for generating the reference signal.

11. The method as claimed in claim 10 , further sampling and holding the detection signal to generate a hold signal for generating the reference signal in response to the hold signal and an amplifier coefficient.

12. The method as claimed in claim 10 , further comprising:

generating a first sample signal in accordance with a rising edge of the detection signal; and

generating a second sample signal in accordance with a falling edge of the detection signal;

wherein the first sample signal and the second sample signal are utilized to control the sampling and holding of the detection signal for generating the reference signal.

13. The method as claimed in claim 9 , further comprising;

comparing the detection signal with the reference signal to generating a switching signal; and

generating the control signal in response to the switching signal.

14. The method as claimed in claim 9 , wherein the detection signal is generated by present switching period of the power converter, and the reference signal is generated by sampling and holding the detection signal generated by previous switching period of the power converter.

15. The method as claimed in claim 9 , wherein the detection signal is correlated to an input voltage of the power converter.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620 FRAME 0087 REEL040075 FRAME 0644 REEL 046410 FRAME 0933 REEL 046530 FRAME 0460 Recorded Sep 18, 2018
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 047103/0575 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded May 2, 2016
From: SYSTEM GENERAL CORP.
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 038594/0168 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2011
From: HSU, JHIH-DA; YEH, CHIA-YO; WANG, CHOU-SHENG; SU, YING-CHIEH; LU, RUI-HONG
To: SYSTEM GENERAL CORP.
Reel/Frame 026012/0266 →