IP Library Granted Patent US 8,304,777
Granted Patent B2
US 8,304,777 · App. 13/069,664 · Granted Nov 6, 2012

Display apparatus, method of manufacturing display apparatus, and electronic apparatus

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Quick Facts
Patent No.
US 8,304,777
App. No.
13/069,664
Granted
Nov 6, 2012
Kind
B2
Abstract

A display apparatus includes a plurality of pixels each including an electro-optic element, a writing transistor writing a video signal into the pixel, a holding capacitor holding the video signal written by the writing transistor, and a driving transistor driving the electro-optic element based on the video signal held in the holding capacitor. The driving transistor includes a channel region, a gate electrode disposed opposite to the channel region, a first source/drain region closer to a power source, a second source/drain region closer to the electro-optic element, and impurity regions disposed between the channel region and the first and second source/drain regions and having a lower concentration than that of the corresponding source/drain region. The impurity region disposed between the channel region and the first source/drain region is formed in a region other than a region facing the gate electrode.

Claims (13)

1. A display apparatus comprising a plurality of pixels each pixel including an electro-optic element, a writing transistor to write a video signal into the pixel, a holding capacitor to hold the video signal written by the writing transistor, and a driving transistor to drive the electro-optic element based at least in part on the video signal held in the holding capacitor, wherein the driving transistor includes:

a channel region,

a gate electrode disposed opposite to the channel region,

a first source/drain region closer to a power source,

a second source/drain region closer to the electro-optic element, and

impurity regions disposed between the channel region and the first and second source/drain regions and having a lower concentration than that of the corresponding source/drain regions, and

wherein the impurity region disposed between the channel region and the first source/drain region is formed in a region other than a region facing the gate electrode;

wherein a part of the impurity region disposed between the channel region and the second source/drain region is formed in a region facing the gate electrode.

2. The display apparatus according to claim 1 , wherein the driving transistor is a bottom gate type transistor in which the gate electrode is disposed closer to a substrate than the channel region.

3. The display apparatus according to claim 2 ,

wherein there is a parasitic capacitance between the gate electrode and the impurity region disposed between the channel region and the second source/drain region, and

wherein a capacitance value of the parasitic capacitance is one of multiple parameters used to determine a gain in a bootstrap operation in which a gate potential is varied on a track of a source potential of the driving transistor when the writing transistor is in a non-conductive state.

4. The display apparatus according to claim 3 , wherein the source potential of the driving transistor is varied according to a current flowing in the driving transistor.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036106/0355 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2011
From: OMOTO, KEISUKE
To: SONY CORPORATION
Reel/Frame 026020/0181 →