IP Library Granted Patent US 8,207,789
Granted Patent B2
US 8,207,789 · App. 13/070,151 · Granted Jun 26, 2012

Differential amplifier circuit

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Quick Facts
Patent No.
US 8,207,789
App. No.
13/070,151
Granted
Jun 26, 2012
Kind
B2
Abstract

Provided is a differential amplifier circuit with a small circuit size. When a differential voltage (Vinp−Vinn) is higher than a predetermined voltage, a PMOS transistor ( 4 ) is turned ON. At this time, a current source ( 12 ) is connected in parallel to a current source ( 11 ), and the current source ( 12 ) supplies a drive current to a differential amplifier circuit ( 10 ). In other words, the current sources ( 11 and 12 ), rather than only the current source ( 11 ), supply a total current (I 11 +I 12 ) to the differential amplifier circuit ( 10 ) as the drive current. Accordingly, a slew rate of an output voltage (Vout) is increased. Two PMOS transistors and the current source ( 12 ) are simply required for controlling the slew rate of the output voltage (Vout), and hence the differential amplifier circuit ( 10 ) is small in circuit size.

Claims (20)

1. A differential amplifier circuit, comprising:

a current mirror circuit which includes a first terminal and a second terminal and is provided to a first power supply terminal;

a first current source provided between a first node and a second power supply terminal;

a first transistor of second conductivity type, including a gate connected to a second input terminal, a source connected to the first node, and a drain connected to the first terminal of the current mirror circuit;

a second transistor of the second conductivity type, including a gate connected to a first input terminal, a source connected to the first node, and a drain connected to the second terminal of the current mirror circuit;

a second current source;

a first transistor of first conductivity type, including a gate connected to the second input terminal, a source connected to the first node, and a drain connected to the second power supply terminal via the second current source; and

a second transistor of the first conductivity type, including a gate connected to the first input terminal, a source connected to the first node, and a drain connected to the second power supply terminal via the second current source.

2. The differential amplifier circuit according to claim 1 , further comprising:

a third current source;

a third transistor of the first conductivity type, including a gate connected to the second input terminal, a source connected to the first node, and a drain connected to the second power supply terminal via the third current source, the third transistor having a threshold voltage different from threshold voltages of the first transistor of the first conductivity type and the second transistor of the first conductivity type; and

a fourth transistor of the first conductivity type, including a gate connected to the first input terminal, a source connected to the first node, and a drain connected to the second power supply terminal via the third current source, the fourth transistor having a threshold voltage different from the threshold voltages of the first transistor of the first conductivity type and the second transistor of the first conductivity type.

3. The differential amplifier circuit according to claim 1 , wherein the current mirror circuit further comprises:

a fifth transistor of the first conductivity type, including a source connected to the first power supply terminal and a drain connected to the first terminal of the current mirror circuit; and

a sixth transistor of the first conductivity type, including a gate connected to a gate and the drain of the fifth transistor of the first conductivity type and to the first terminal of the current mirror circuit, a source connected to the first power supply terminal, and a drain connected to the second terminal of the current mirror circuit.

4. The differential amplifier circuit according to claim 2 , wherein the current mirror circuit further comprises:

a fifth transistor of the first conductivity type, including a source connected to the first power supply terminal and a drain connected to the first terminal of the current mirror circuit; and

a sixth transistor of the first conductivity type, including a gate connected to a gate and the drain of the fifth transistor of the first conductivity type and to the first terminal of the current mirror circuit, a source connected to the first power supply terminal, and a drain connected to the second terminal of the current mirror circuit.

5. The differential amplifier circuit according to claim 3 , wherein the first transistor of the first conductivity type and the second transistor of the first conductivity type each have a threshold voltage different from threshold voltages of the fifth transistor of the first conductivity type and the sixth transistor of the first conductivity type.

6. The differential amplifier circuit according to claim 4 , wherein the first transistor of the first conductivity type and the second transistor of the first conductivity type each have a threshold voltage different from threshold voltages of the fifth transistor of the first conductivity type and the sixth transistor of the first conductivity type.

Assignments (5)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2011
From: TSUZAKI, TOSHIYUKI
To: SEIKO INSTRUMENTS INC.
Reel/Frame 026007/0432 →