ESD protection device having a geometric salicide pattern
View Patent ↗Provided is a semiconductor device having an ESD protection MOS transistor including a plurality of transistors combined together, in which a plurality of drain regions and a plurality of source regions disposed alternately and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, in which a distance between a salicide metal region, which is formed on each of the plurality of drain regions, and the gate electrode is determined according to contact holes in the plurality of drain regions and a distance of the contact holes from substrate contacts.
1. A semiconductor device, comprising an ESD protection MOS transistor in a substrate and spaced apart from substrate contacts, the ESD protection MOS transistor comprising:
a plurality of drain regions and a plurality of source regions disposed alternately; and
a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, thereby constitutes a unified structure;
wherein the plurality of drain regions are electrically connected to an external connection terminal,
wherein the plurality of source regions are electrically connected to a ground electric potential supplying line, and
wherein each of the plurality of drain regions is provided with a salicide metal pattern on a surface of the substrate, such that a distance along the surface of the substrate between an edge of the salicide metal pattern and the gate electrode and a corresponding transistor resistance between a nearest contact hole and the gate electrode steadily decreases as a distance along the surface of the substrate from the salicide metal pattern to the substrate contacts of the ESD protection MOS transistor increases.
2. The semiconductor device according to claim 1 , wherein, when each of the plurality of drain regions comprises a plurality of rows of contact holes, each contact hole is kept at a constant distance from a nearest edge of the salicide metal.
3. The semiconductor device according to claim 1 , wherein the salicide metal pattern contains one of Ti and Co.
4. The semiconductor device according to claim 1 , wherein the substrate contacts comprise a linear pattern surrounding the ESD protection MOS transistor.
5. A semiconductor device, comprising an ESD protection MOS transistor in a substrate, the ESD protection MOS transistor comprising:
a plurality of drain regions and a plurality of source regions disposed alternately; and
a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, thereby constitutes a unified structure;
wherein the plurality of drain regions are electrically connected to an external connection terminal,
wherein the plurality of source regions are electrically connected to a ground electric potential supplying line, and
wherein each of the plurality of drain regions is provided with a salicide metal pattern on a surface of the substrate, such that a distance along the surface of the substrate between an edge of the salicide metal pattern and the gate electrode and a corresponding transistor resistance between a nearest contact hole and the gate electrode steadily decreases as a distance along the surface of the substrate between the external connection terminal and the ESD protection MOS transistor increases.
6. The semiconductor device according to claim 5 , wherein, when each of the plurality of drain regions comprises a plurality of rows of contact holes, each contact hole is kept at a constant distance from a nearest edge of the salicide metal pattern.
7. The semiconductor device according to claim 5 , wherein the salicide metal pattern contains one of Ti and Co.
8. The semiconductor device according to claim 5 further comprising substrate contacts in a linear pattern surrounding the ESD protection MOS transistor, and wherein the substrate contacts reside between the external connection terminal and ESD protection MOS transistor along the substrate surface.